LPC553x/S3x: Advanced Analog Arm®Cortex®-M33-Based MCU Family

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The LPC553x/S3x MCU family further expands the general purpose Cortex-M33-based MCU series, offering significant performance enhancement, all on-chip RAM with Parity or ECC, renewed security features and precision analog additions, leveraging the cost-effective 40-nm NVM process technology.

The LPC553x/S3x family includes a proprietary DSP accelerator offering 10x clock cycle reduction, bringing significant signal processing efficiency gains.

Block Diagram

LPC553x/55S3x MCU

LPC55S3x 3x BD New
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Features

Arm® Cortex®-M33 Core (r0p4)

  • Running at a frequency of up to 150 MHz
  • Integrated digital signal processing (DSP) instructions
  • Floating point unit (FPU) and memory protection unit (MPU)
  • Arm Cortex M33 built-in nested vectored interrupt controller (NVIC)
  • Non-maskable interrupt (NMI) input with a selection of sources
  • Serial Wire Debug with eight breakpoints and four watch points. Includes Serial Wire Output for enhanced debug capabilities and trace (ETM)
  • System tick timer

DSP Accelerator/Coprocessor

  • A hardware DSP accelerator for fixed- and floating-point DSP functions (PowerQuad)
    • The PowerQuad uses a bank of four dedicated 4 kB SRAM
  • Crypto/FFT engine (public key cryptography (PKC))
    • PKC uses a bank of 4 KB SRAM that is also AHB accessible by the CPU and the DMA engine

On-Chip Memory

  • Up to 256 kB on-chip flash program memory with flash accelerator, 8 kB low-power cache and 512 byte page erase and write
  • Up to 128 kB total SRAM consisting of 16 kB SRAM on code bus, 112 kB SRAM on system bus (112 kB is contiguous)
    • 112 kB has Parity and 16 kB ECC SRAM

Security Features

  • Arm TrustZone® enabled
  • PRINCE module for real-time encryption of data being written to off-chip flash and decryption of encrypted flash data during read to allow asset protection such as securing application code and enabling secure flash update. External memory can be encrypted and the content being decrypted on-the-fly while the controller is fetching data from the external memory.
  • AES-256 encryption/decryption engine with keys fed directly from PUF or software supplied key. Supports AES-GMAC mode.
  • Secure Hash Algorithm (SHA2) module supporting secure boot with a dedicated DMA controller.
  • Physical unclonable function (PUF) using dedicated SRAM for silicon fingerprint. PUF can generate, store and reconstruct key sizes from 64 bits to 4096 bits; includes hardware for key extraction*
  • 128-bit unique device serial number for identification (UUID)
  • Secure GPIO
  • True random number generator (TRNG)
  • Secure Boot support
  • Code Watchdog for detecting code flow integrity
  • Device Identifier Composition Engine (DICE)
  • On-chip ROM bootloader supports:
    • Booting of images from on-chip flash and external flash
    • CRC32 image integrity checking
  • Flash programming through in system programming (ISP) commands over the following interfaces:
    • USB0 interfaces using HID Class device
    • UART interface (Flexcomm 0) with auto baud
    • High-Speed SPI responder interfaces (Flexcomm 8) using mode 3 (CPOL = 1 and CPHA = 1)
    • I²C responder interface (Flexcomm 1)
    • CAN FD ISP
  • ROM API functions:
    • Flash programming API
    • Power control API
    • OTP programming API
    • Protected flash region (PFR) programming
    • Secure firmware update API using NXP Secure Boot file format, version 3.1 (SB3 files)
  • Booting of images from PRINCE encrypted flash regions and IPED encrypted external flash.
  • NXP Debug Authentication Protocol version 1.0 (RSA-2048), 1.1 (RSA-4096) and version 2.0 (ECDSA-256, UUID in DAR)
  • Setting a sealed part to Fault Analysis mode through Debug authentication
  • Dual images (boot latest version) from on-chip flash using remap feature
  • Loading image to RAM from an external Octal/QuadSPI device.
  • Booting execute-in-place (XIP) images present on Octal/QuadSPI devices
  • Dual execute-in-place (XIP) images in Octal/QuadSPI flash through flash address remap feature
  • Load-to-RAM boot mode from 1-bit SPI flash devices connected to Flexcomm (selectable by PFR) as normal boot option and recovery boot option
  • USB Device DFU Connection (device only)
  • Code read protection (CRP) on non-secure devices
  • Crystal-less USB ISP Device mode
  • Secure Boot support:
    • RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic signature verification
    • RSA-2048 bit public keys (2048-bit modulus, 32-bit exponent)
    • RSA-4096 bit public keys (4096-bit modulus, 32-bit exponent)

Serial Interfaces

  • The FlexComm interface contains up to eight serial peripherals. Each FlexComm interface can be selected by software to be a USART, SPI, I²C and I²S interface. A variety of clocking options are available to each Flexcomm Interface, including a shared fractional baud-rate generator and time-out feature. Flexcomm interfaces 0 to 5 each provide one channel pair of I²S and Flexcomm interfaces 6 to 7 each provide four channel pairs of I²S.
  • I²C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1 Mbit/s and with multiple address recognition and monitor modes. Two sets of true I²C pads also support high-speed mode (3.4 Mbit/s) as a responder
  • High-speed SPI (Flexcomm 8, 50 MHz for both controller and responder)
  • A digital microphone interface supporting up to two channels with associated decimators and voice activation detect. One pair of channels can be streamed directly to I²S. The DMIC supports DMA.
  • One I³C bus interface
  • One CAN FD module with dedicated DMA controller
  • USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode

Digital Peripherals

  • DMA0 controller with 52 channels and up to 53 programmable triggers, able to access all memories and DMA-capable peripherals
  • DMA1 controller with 16 channels and up to 25 programmable triggers, able to access all memories and DMA-capable peripherals
  • CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support
  • Up to 66 general-purpose input/output (GPIO) pins
  • GPIO registers are located on the AHB for fast access; the DMA supports GPIO ports
  • Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or both input edges
  • Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states
  • I/O pin configuration with support for up to 16 function options
  • FlexSPI flash interface for external flash with 8 kB cache and dynamic decryption for execute-in-place and supports DMA. The FlexSPI includes 1 port: high-speed channel A, which supports quad or octal operation. Support dual image via address remapping.
  • Two AOI (AND/OR/Invert) combinatorial logic modules with a dedicated set of input and output signals; each AOI has 4 outputs that feed to different peripheral muxes to individual peripherals

Analog Peripherals

  • Four single-ended 16-bit or two-differential input ADCs (selectable) with sample rate of 2.0 Msamples/sec in 16-bit mode and 3.13 Msamples/sec in 12-bit mode. Eight differential channel pairs (or 16 single-ended channels), with multiple internal and external trigger inputs. The ADC supports four simultaneous conversions, under the control of two independent sequences
  • Integrated temperature sensor connected to both ADCs
  • One comparator in an always-on domain with up to four input pins and internal reference voltage; can be used as a wake-up source from low-power modes
  • Three high-speed comparators with up to five input pins and internal reference voltage
  • Three 12-bit DACs with sample rates of up to 1.0 Msamples/sec
  • Three OpAmps with programmable VREF
  • Programmable VREF

Motor Control Subsystems

  • 2x FlexPWM with 4 submodules, providing 12 PWM outputs and 2 Quadrature Encoder/Decoder (QEI).

Timers

  • Five 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs; specific timer events can be selected to generate DMA requests
  • One SCTimer/PWM with eight input and ten output functions (including 16 capture and match). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16 events, 32 states and a Dither engine for improved average resolution of pulse edges.
  • 32-bit real-time clock (RTC) with calendar feature and 1 s resolution running in the always-on power domain A timer in the RTC can be used for wake-up from all low-power modes including deep power-down with 1 ms resolution. The RTC is clocked by the 32 kHz FRO or 32.768 kHz external crystal.
  • Multiple-channel multirate 24-bit timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates
  • Windowed watchdog timer (WWDT) with FRO 1 MHz as a clock source
  • Micro-tick timer running from the watchdog oscillator can be used to wake up the device from sleep and deep-sleep modes; includes 4 capture registers with pin inputs
  • Code Watchdog for detecting code flow integrity
  • 42-bit free running OS timer as a continuous timebase for the system, available in any reduced power modes. It has a selectable clock source. When a 32 kHz clock is selected, allow a count period of more than 4 years

Clock Generation

  • Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96 MHz output, and a 12 MHz output (divided down from the selected higher frequency) that can be used as a system clock. The FRO is trimmed to +/- 1% accuracy over the entire voltage and 0 C to 85 C. The FRO is trimmed to +/- 2% accuracy over the entire voltage and -40 C to 105 C.
  • 32 kHz internal free Running oscillator FRO, which is trimmed to +/- 2% accuracy over the entire voltage and temperature range
  • Internal low-power oscillator (FRO 1 MHz) trimmed to +/- 15% accuracy over the entire voltage and temperature range
  • Crystal oscillator with an operating frequency of 12 MHz to 32 MHz; option for external clock input (bypass mode) for clock frequencies of up to 25 MHz
  • Crystal oscillator with 32.768 kHz operating frequency
  • PLL0 and PLL1 allow CPU operation up to the maximum CPU rate without the need for a high-frequency external clock. PLL0 and PLL1 can run from the internal FRO 12 MHz output, the external oscillator, internal FRO 1 MHz output, or the 32.768 kHz RTC oscillator
  • Clock output function with divider to monitor internal clocks
  • Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal
  • Each crystal oscillator has one embedded capacitor bank, where each can be used as an integrated load capacitor for the crystal oscillators. Using APIs, the capacitor banks on each crystal pin can tune the frequency for crystals with a capacitive Load (CL) leading to conserving board space and reducing costs.

Power-Saving Modes

  • Integrated power management Unit (PMU) to minimize power consumption
  • Low power modes: sleep, deep-sleep with RAM retention, power-down with RAM retention and CPU retention and deep power-down with RAM retention.
  • Configurable wake-up options from peripheral interrupts
  • The Micro-Tick Timer running from the watchdog oscillator, and the Real-Time Clock (RTC) running from the 32.678 kHz clock, can be used to wake up the device from sleep, deep-sleep, power-down and deep power-down modes
  • Power-on reset (POR)
  • Brown-out-detect (BOD) for external VDD_MAIN and internal VDD_CORE with separate thresholds for interrupt and forced reset

Additional Information

  • Operating from an internal DC-DC converter or selectable LDO such that DC-DC converter can be bypassed
  • Single power supply 1.8 V to 3.6 V
  • Two main IO supplies (VDDIO_1: 1.8 V to 3.6 V, VDDIO_2: 1.08 V to 3.6 V)
  • Separate VBAT supply 1.71 V to 3.6 V.
  • JTAG boundary scan supported
  • Operating temperature range -40 °C to +105 °C
  • Available in HLQFP100, HTQFP64 and HVQFN48 packages

Buy/Parametrics

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