8-bit General Purpose GT MCUs

Block Diagram

NXP S08GT Microcontroller Block Diagram

Freescale S08GT Microcontroller Block Diagram

Features

8-bit HCS08 CPU Core

  • Low-power technology
    • Multiple power management modes, including 20 nA powerdown
    • Optional autowake-up from Stop 2 or Stop 3 modes with internal timer typically requires only 300 nA additional current
    • 1.8V operation
  • High performance when needed
    • 50 ns minimum instruction cycle time down to 2.1V at 20 MHz bus
    • 125 ns minimum instruction cycle time down to 1.8V at 8 MHz bus
  • C-optimized architecture with multiply and divide instructions

On-Chip Debug Interface

  • Single-wire background debug mode
  • On-chip trace buffer with nine flexible trigger modes and multiple hardware breakpoints
  • Nonintrusive emulation

Integrated Third-Generation Flash Memory

  • In-application reprogrammable
  • Self-timed, fast programming
    • Can program 8 bits in 20 µs
    • Fast flash page erase of 20 ms (512B)
  • 10K write/erase cycles minimum, 100K typical
  • 15-year minimum data retention, 100 years typical
  • Internal program/erase voltage generation
  • Fine Flash granularity—512B Flash erase/1B Flash program
  • Flexible block protection and enhanced security

Internal Clock Generator

  • High gain oscillator option
  • Programmable frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates up to 20 MHz)
  • Post-FLL divider gives one of eight bus rate dividers
  • Trimmable with temperature and voltage compensation (<2 percent drift)
  • Provides multiple options for clock sources and in-application clock switching
    • 32 kHz to 16 MHz external crystal/resonator
    • Internal clock generator
    • External clock

10-bit Analog-to-Digital Converter (ADC)

  • Eight-channel ADC
  • 14 µs, 10-bit single conversion time

Timer with Five Programmable Channels

  • 1 x 3 channel, 1 x 2 channel, 16-bit timer systems
  • Each channel programmable for
    • Input capture, output compare or buffered pulse-width modulator (PWM)
    • PWM can be edge- or center-aligned
  • 16-bit free-running or up/down (CPWM) count operation
  • Flexible, programmable timer system

Extensive Serial Communications

  • Dual asynchronous SCIs
    • Flexible 13-bit module-based baud rate generators
    • Double-buffered receive and transmit
  • Synchronous SPI up to 5 Mbps
  • Inter-IC (I²C) bus
    • Multicontroller operation
    • 256 clock options

System Protection

  • Selectable low-voltage detect/reset at nominal 1.8V
  • Low-battery warning at nominal 2.4V or 2.1V
  • COP watchdog timer
  • Loss of clock detect (LOCD) (with option to disable for lower power consumption)

Up to 39 Input/Output (I/O) Lines

  • Programmable pull-ups
  • High-current drivers
  • Eight keyboard interrupts
  • Controlled rise/fall times minimize noise

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Documentation

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1-10 of 70 documents

Compact List

Application Note (25)
Application Note Software (12)
Brochure (1)
Data Sheet (4)
Errata (8)
Fact Sheet (3)
Product Change Notice (2)
Reference Manual (2)
Reliability and Quality Information (3)
Technical Notes (8)
User Guide (2)

Design Files

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1 design file

Hardware

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Software

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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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