Integrated Multi-Protocol Processor

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Product Details

Block Diagram

Integrated Multi-Protocol Processor Block Diagram

Integrated Multi-Protocol Processor Block Diagram

Features

  • MC68000/MC68008 Microprocessor Core
  • Efficient architecture involves a separate RISC processor for handling communications
  • Three Serial Communications Controllers (SCCs)
  • Support for HDLC/SDLC, Bisync, UART, DDCMP, and Totally Transparent protocols.
  • Two Serial Management Controllers (SMCs) for IDL and GCI Channel.
  • Available at 16, 20, 25, and 33 MHz in three different Thin Quad Flat Pack Packages.
  • Strong 3rd Party tools support.
  • ISDN equipment
  • Data Concentrators
  • Modems
  • Line Cards
  • Network Bridges
  • Gateways
  • MC68000/MC68008 Microprocessor Core (May be disabled to use the IMP as a peripheral)
  • SIB Including:
    • Independent Direct Memory Access (IDMA) Controller
    • Interrupt controller with two modes of operation
    • Parallel I/O ports, some with interrupt capability
    • On-Chip 1152-bytes of dual-port RAM
    • Three timers, with a software watchdog timer
    • Four programmable chip-select lines with wait-state logic
    • Programmable address mapping of dual-port RAM and IMP registers
  • On-Chip clock generator with an output clock signal
  • System Control
    • Bus arbitration logic with low interrupt latency support
    • System control register
    • Hardware watchdog for monitoring bus activity
    • Low power (Standby) modes
    • Disable CPU logic (M68000)
    • Freeze control for debugging selected on-chip peripherals
    • DRAM refresh controller
  • CP Including:
    • Main controller (RISC Processor)
    • Three full-duplex Serial Communication/Controllers with the following protocols:
      • HDLC/SDLC
      • Bisync
      • UART
      • DDCMP
      • Totally Transparent
      • V.110
    • Six serial DMA channels dedicated to the three SOCs
    • Capability to send/receive up to eight buffers/frames without M68000 core intervention
    • Flexible physical interface accessible by SCCs for Inter-chip Digital Link (IDL), General Circuit Interface (GCI).
    • Pulse Code Modulation (PCM), and Non-multiplexed Serial Interface (NMSI) Operation.
    • Serial Communication Port (SCP) for synchronous communication.
    • Two Serial Management Controllers (SMCs) for IDL and GCI Channel.

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Documentation

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1-10 of 60 documents

Compact List

Application Note (12)
Data Sheet (6)
Errata (12)
Fact Sheet (1)
Package Information (5)
Product Brief (1)
Product Change Notice (3)
Reference Manual (16)
Supporting Information (1)
Technical Notes (1)
User Guide (2)

Design Files

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3 design files

Software

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