Quad Integrated Communication Controller (QUICC)

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The MC68360 Quad Integrated Communication Controller (QUICC™) is a versatile one-chip integrated microprocessor and peripheral combination family that can be used in a variety of controller applications.

The MC68360 particularly excels in communications activities. The QUICC can be described as a next-generation MC68302, with higher performance in all areas of device operation, increased flexibility, and higher integration. The term "quad" comes from the fact that there are four serial communications controllers (SCCs) on the device. However, there are actually seven serial channels which include four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).

Data Sheet

Reference Manual

Product Details

Block Diagram

Quad Integrated Communication Controller Block Diagram

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Features

32-bit version of the CPU32 core (fully compatible with CPU32)

Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address Lines
Complete static design (0-33 MHz Operation)
Follower mode to disable CPU32+ (allows use with external processors)
- Multiple QUICCs can share one system bus (one leader)
- MC68040 companion mode allows QUICC to be an MC68040 companion chip and intelligent peripheral (29 MIPS at 33 MHz)
- All QUICC features available in follower mode
Memory controller (eight banks)
- Contains complete Dynamic Random-Access Memory (DRAM) controller
- Glueless interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random-Access Memory (SRAM),
- Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc.
- Boot chip select available at Reset (options for 8-, 16-, or 32-bit memory)
- Special features for MC68040 including Burst Mode
Four general-purpose timers
- Four 16-bit timers or two 32-bit timers
Two Independent DMAs (IDMAs)
System Integration Module (SIM60)
- Bus monitor
- Breakpoint logic provides on-chip H/W breakpoints
- Spurious interrupt monitor
- External leaders may use on-chip features such as chip selects
- Periodic interrupt timer
- On-chip bus arbitration with no overhead for internal leaders
- Low power stop mode
- IEEE 1149.1 Test Access Port
RISC Communications Processor Module (CPM)
- Many new commands (e.g., Graceful Stop Transmit, Close RxBD)
- Supports continuos mode transmission and reception on all serial channels
- 2.5 kbytes of dual-port RAM
- 14 Serial DMA (SDMA) channels
- Three parallel I/O registers with open-drain capability
- Each serial channel can have its own Pins (NMSI mode)
Four baud rate generators
Four SCCs
- Ethernet/IEEE 802.3 optional on SCCs 1-2@25 MHz, SCCs 1-3@33 MHz
- HDLC Bus
- Universal Asynchronous Receiver Transmitter (UART)
- Synchronous UART
- Asynchronous HDLC (RAM microcode option) to support PPP (Point to Point Protocol)
Two SMCs
- UART
- Transparent
- General Circuit Interface (GCI) controller
One SPI
Time-Slot assignor
Supports two TDM channels
Parallel Interface Port (supports fast connection between QUICCs)

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Design Resources

Design Files

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2 design files

Receive the full breakdown. See the product footprint and more in the eCad file.

Printed Circuit Boards and Schematics
BDM Interface Schematics

ZIPDec 4, 1996 00:00:0080.8 KBMC68360SCH1

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Printed Circuit Boards and Schematics
MC68040 and Two MC68360 Demo Board Schematics (QUEEN)

ZIPDec 4, 1996 00:00:00120.0 KBMC68360SCH2

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Software

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3 software files

Libraries
Complimentary ColdFire^® Digital Signal Processing LibraryFeatured
Application Example Software
Software Bundled with QUICC Application Development System (QUADS)

ZIPRev 0Jul 3, 1997 00:00:001.5 MBMC68360ADF2

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Development IDEs and Build Tools
CodeWarrior^® Development Studio for 68K Embedded Systems (Classic IDE) v3.2

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Quad Integrated Communication Controller (QUICC)

Product Details

Block Diagram

Quad Integrated Communication Controller Block Diagram

Features

Buy/Parametrics

Documentation

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Application Note (20)

AN2046 MC68360 Interfacing SDRAM to the MC68360 QUICC Device[AN2046]

AN2036 MC68360 Multiple Ethernet Channels on the QUICC[AN2036]

AN2039 MC68360 Bus Arbitration PAL for a 68040 and two 360s[AN2039]

MC68360 Multiple QUICC Design Concept[AN2032]

AN2042 MC68360 Proper Functioning of Autobaud Feature[AN2042]

MC68360 Interfacing the QUICC to a MCM516400 (4Mx4 10/12 column/row) DRAM[AN2030]

MC68360 GSMR Register Effect on SCC in Transparent Mode[AN2034]

AN2049 MC68302, MC68360, and MPC860 Characteristics and Design Notes for Crystal Feedback Oscillators[AN2049]

MC68360 Implementing an 8 bit Eprom for an MC68EC040/MC68360 System[AN2035]

Differences Between the MC68360 and the MPC860[AN2050]

Porting Code from MC68360 to MPC860[AN2051]

AN2044 MC68360 How to Connect Multiple S/T or U ISDN Interfaces to a QUICC32[AN2044]

AN2043 MC68360 EC020/683XX Interface to ISA Bus-Type PCMCIA Controller[AN2043]

AN2040 MC68360 RAM Microcode Package Option Overview[AN2040]

AN2045 MC68360 CPM/CPU Interaction[AN2045]

AN2041 MC68360 Evaluating the MC68360 Serial Performance[AN2041]

AN2029 QUICC Ethernet Address Filtering with DSP56002[AN2029]

AN2037 MC68360 Applications Information - Interfacing the MC68EN360 to an Ethernet SIA[AN2037]

AN2031 Interfacing the 68360 QUICC to T1/E1 Systems[AN2031]

AN2038 MC68360 Interfacing the MC68060 to the MC68360[AN2038]

Data Sheet (5)

Thermal Measurement Report - Data Sheet[MC68360THERMAL]

MC68360 New Features on REV C.1[MC68360C1]

MC68360 New Features on REV B[MC68360B]

MC68360TUT[MC68360TUT]

MC68360 Quad Integrated Communication Controller Product Brief[MC68360]

Errata (6)

M68360 Device Errata - MC68360 QUICC[MC68360DEC1]

M68360 Device Errata - MC68360 QUICC[MC68360DEC0]

M68360 Device Errata - MC68MH360 QUICC32[MC68MH360DEC1]

M68360 Device Errata - MC68MH360 QUICC32[MC68MH360DEE1]

M68360 Device Errata - MC68360 QUICC[MC68360DEB4]

M68360 Device Errata - MC68360 QUICC[MC68360DEB2]

Fact Sheet (1)

MC68360 QUAD INTEGRATED COMMUNICATION CONTROLLER ( QUICC ™ ) - Fact Sheet[MC68360FACT]

Package Information (7)

PBGA Packaging Customer Tutorial[PBGAPRES]

MC68360 BGA Pin Assignment[MC68360BGA]

MC68360 PGA Pin Assignment[MC68360PGA]

MC68360/MC68EN360 240-pin QFP Pin Assignment[MC68360QFP]

MC68360 BGA Part Symbol (OrCAD Capture 7.1+)[MC68360BGA_OLB]

MC68360/MC68EN360 240-pin QFP Part Symbol (OrCAD Capture 7.1+)[MC68360QFP_OLB]

MC68360 PGA Part Symbol (OrCAD Capture 7.1+)[MC68360PGA_OLB]

Product Change Notice (2)

MC68360 Rev L fab transfer to TSC-PCN5635[PCN5635]

68MH360 Mask Revision-PCN5852[PCN5852]

Reference Manual (3)

Archived 2005 - MC68360 Quad Integrated Communication Controller User's Manual[MC68360UM]

MC68360 QMC Supplement to MC68360 and MPC860 Users Manuals[MC68MH360UM]

Archived 2005 - MC68360 Errata and Added Information to MC68360 Quad Integrated Communication Controller User's Manual[MC68360UMAD]

User Guide (4)

MC68360 ATOM1: MC68360 ATM Microcode User's Manual[MC68360ATOM1UM]

MC68360 Asynchronous HDLC - MC68360 ASYNC HDLC Protocol Microcode User's Maunal[MC68360AHDLCUM]

MC68360 Signaling System 7 MC68360 SS7 Protocol Microcode User's Manual[MC68360SS7UM]

MC68360QUADS Hardware User's Manual[MC68360QUADSUM]

Design Resources

Design Files

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BDM Interface Schematics

MC68040 and Two MC68360 Demo Board Schematics (QUEEN)

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Software

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Complimentary ColdFire® Digital Signal Processing LibraryFeatured

Software Bundled with QUICC Application Development System (QUADS)

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Complimentary ColdFire^® Digital Signal Processing LibraryFeatured