PowerQUICC® III Processor with DDR2/3, Pattern Matching Engine, PCI Express®

  • This page contains information on a product that is not recommended for new designs.

Block Diagram

MPC8572 Block Diagram

Features

  • Dual e500 Power Architecture cores scaling to 1.5 GHz
  • 1 MB L2 cache/SRAM with I/O stashing
  • 32 KB I/D L1 cache per core
  • Dual integrated DDR2/DDR3 SDRAM memory controllers
    • 64-bits (72-bits with ECC) per controller
    • to 800 MHz datarate
  • Four integrated Ethernet controllers (enhanced TSEC)
    • 10/100/1000 support
    • TCP/UPD offload
    • Quality of service support
    • IEEE® 1588 support
    • Lossless flow control
    • SGMII interfaces
  • Single 10/100 fast Ethernet controller (FEC) with MII (muxed)
  • TLU offloading complex table searches
  • Pattern matching engine searches for regular expressions within packet payloads
    • Includes packet deflate engine to expose zipped payloads
  • Security engine
    • DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms
  • PCI Express®
  • Serial RapidIO®
  • 32-bit local bus running up to 133 MHz
  • Dual I²C, Dual DMA, DUART, multiprocessor interrupt controller, IEEE1149.1 JTAG test access port
  • 1023-pin FC-PBGA package
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

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Documentation

Quick reference to our documentation types.

1-10 of 59 documents

Compact List

Application Note (33)
Application Note Software (3)
Data Sheet (1)
Fact Sheet (1)
Package Information (1)
Quick Reference Guide (1)
Reference Manual (6)
Supporting Information (2)
User Guide (2)
White Paper (9)

Design Files

Hardware

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2 hardware offerings

Software

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2 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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Training

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Support

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