PowerQUICC® III Processor with DDR2, PCI, PCI Express®, Serial RapidIO, SerDes, 1 GB Ethernet, Security

  • This page contains information on a product that is not recommended for new designs.

Block Diagram

NXP PowerQUICC MPC8548E Communications Processor Block Diagram

PowerQUICC<sup>&#174;</sup> MPC8548E Communications Processor Block Diagram

Features

  • Embedded e500 core, scaling up to 1.5 GHz
    • Dual dispatch super-scaler, 7-stage pipeline design with out-of-order issue and execution
    • 3065 MIPS at 1333 MHz (estimated Dhrystone 2.1)
  • Integrated L1/L2 cache
    • L1 cache -32 KB data and 32 KB instruction cache with line-locking support
    • L2 cache -512 KB (8-way set associative); 512 KB/256 KB/128 KB/64 KB can be used as SRAM
    • L1 and L2 hardware coherency
    • L2 configurable as SRAM, cache or stash cache
  • Integrated DDR memory controller with full ECC support, supporting:
    • 200 MHz clock rate (400 MHz data rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM
    • 266 MHz clock rate (up to 533 MHz data rate) DDR2 SDRAM
  • Double-precision embedded scalar and vector floating-point APUs
  • Memory management unit (MMU)
  • Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms
  • Multiple PCI interface support
    • 64-bit PCI 2.2 bus controller (up to 66 MHz, 3.3V I/O)
    • 64-bit PCI-X bus controller (up to 133 MHz, 3.3V I/O), or
    • Flexibility to configure two 32-bit PCI controllers
  • Four on-chip triple-speed Ethernet controllers (GMACs) supporting 10- and 100-Mbps, and 1-Gbps Ethernet/802.3 networks with MII, RMII, GMII, RGMII, RTBI and TBI physical interfaces.
    • TCP/IP checksum acceleration
    • Advanced QoS features
  • General-purpose I/O
  • Serial RapidIO and PCI Express high-speed interconnect interfaces, supporting
    • Single x8 PCI Express, or
    • Single x4 PCI Express and single 4x Serial RapidIO
  • On-chip network (OCeaN) switch fabric
  • Integrated four-channel DMA controller
  • Dual I²C interfaces and dual universal asynchronous receiver/transmitter (DUART) support
  • Programmable interrupt controller (PIC)
  • General-purpose parallel I/O (GPIO)
  • IEEE® 1149.1 JTAG test access port
  • 1.1V core voltage with 3.3V and 2.5V I/O
  • 783-pin FC-BGA package
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

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Documentation

Quick reference to our documentation types.

1-10 of 64 documents

Compact List

Application Note (35)
Application Note Software (4)
Brochure (1)
Data Sheet (1)
Errata (1)
Fact Sheet (10)
Package Information (1)
Reference Manual (5)
Supporting Information (2)
White Paper (4)

Hardware

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3 hardware offerings

Software

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3 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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Training

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