i.MX RT600 Crossover MCU with Arm® Cortex®-M33 and DSP Cores

i.MX-RT600 Active

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i.MX RT600 Crossover MCUs are dual-core devices featuring an Arm® Cortex®-M33 and Cadence® Xtensa® HiFi4 Audio DSP CPU designed for audio, voice and consumer IoT applications.

The i.MX RT600 Arm® Cortex®-M33 operates at up to 300 MHz and includes two coprocessors providing enhanced performance. The HiFi4 can operate up to 600 MHz. The family offers a rich set of peripherals, embedded security and very low power consumption. The device has up to 4.5 MB SRAM and a FlexSPI with two ports and 32 KB cache.

The i.MX RT600 family is supported by the MCUXpresso ecosystem, which includes an SDK, a choice of IDEs and secure provisioning and configuration tools to enable rapid development.

Block Diagram

i.MX-RT600 Crossover MCU

i.MX RT600 Crossover MCU
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Features

Next-Generation Cortex-M33 Control Processor Core Running at a Frequency Up to 300MHz

  • Arm TrustZone® for asset protection
  • Cortex-M33 built-in memory protection unit (MPU) supporting eight regions
  • Two coprocessors for the Cortex-M33
    • PowerQuad hardware accelerator for (fixed and floating point unit) DSP functions
    • CASPER Crypto coprocessor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms

Highly Optimized Cadence® Tensilica® HiFi 4 DSP Processor Core, Running at Frequencies of Up to 600 MHz

  • Hardware floating point unit, up to to four single-precision IEEE floating point MACs per cycle

Software and Tools

On-Chip Memory

  • Up to 4.5 MB of system SRAM accessible by both CPUs and all DMA engines
  • 128 KB of local, tightly-coupled memory dedicated to the DSP CPU
  • 96 KB of I & D cache for DSP accesses to shared system SRAM

Digital Peripherals

  • Two DMA engines, each with 32 channels
  • Octal/Quad SPI Flash with a dynamic description
  • Two SD/eMMC memory card interfaces, one supporting eMMC 5.0 with HS400/DDR operation
  • USB high-speed host/device controller with on-chip PHY
  • Up to eight configurable universal serial interface modules (Flexcomm Interfaces). Configurable as SPI/I2C/I2S/UART
  • One high-speed SPI interface supporting 50 MHz operation
  • One Enhanced Serial Peripheral Interface (eSPI)
  • One I3C bus interface
  • A digital microphone interface supporting up to 8 channels

Security Features

  • Secure Isolation
    • Secure execution environment through Arm® TrustZone® technology for ARMv8-M
    • Symmetric key isolation through hardware engines
  • Secure Boot
    • Secure boot support implemented in boot ROM, providing immutable root of trust
  • Secure Storage
    • Physically unclonable function (PUF) based key store
    • On-the-fly-AES decryption (OTFAD) of off-chip flash for code storage
  • Secure Debug
    • Certificate-based debug authentication mechanism
  • Secure Update
    • Supports firmware update with authenticity (RSA signed) and confidentiality (AES-CTR encrypted) protection
  • Hardware Cryptography Accelerators
    • Symmetric cryptography (AES) with 256-bit key strength
    • Asymmetric cryptography acceleration
    • TRNG with 256-bit entropy
    • Hash engine with SHA-256 and SHA-1
  • Secure Identity
    • 128-bit universal unique identifier (UUID) and 256-bit compound device identifier (CDI)
  • A member of the EdgeLock Assurance program, providing on-chip security capabilities.

Buy/Parametrics

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