QorIQ® P2020

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P2010 and P2020 devices are "Not recommended for new designs", please use the replacement families Power Architecture (T1013, T1023), Arm Architecture (LS1012A, LS1023A).

The QorIQ^® P2020 and P2010 communications processors deliver high performance per watt for dual- and single-core applications. Using advanced 45nm process technology these CPUs reach frequencies up to 1.33GHz.

Pin-compatible with the QorIQ P1 family devices, the P2020 and P2010 devices offer four interchangeable cost-effective solutions, scaling from a single core at 533 MHz (P1011) to a dual core at 1.33 GHz (P2020) and delivering an impressive 4.5x aggregate frequency range within the same pinout.

Data Sheet

Reference Manual

Product Details

Block Diagram

Freescale QorIQ P2020/10 Communication Processor Block Diagram

Get diagram PDF

Features

Core Complex

Dual (P2020) or single (P2010) high-performance Power Architecture^® e500 cores
Up to 1.33 GHz
32 KB L1 and 512KB L2 caches

Networking Elements

Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
Four SerDes up to 3.125 GHz multiplexed across controllers supporting:
- Two PCI Express^® interfaces
- Two Serial RapidIO^® interfaces
- Two SGMII interfaces

Accelerators and Memory Control

Integrated security engine
Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi, XOR acceleration

Basic Peripherals and Interconnect

Dual high-speed USB controllers (USB 2.0)
eLBC, eSDHC, Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

Package: 689-pin temperature-enhanced plastic BGA (TEPBGA2)
0C to 125C Tj -40C to 125C Tj option

Comparison Table

	P2010	P2020
Cores	1	2
Core Frequency	800 - 1200 MHz	800 - 1200 MHz
L2 Cache	512KB	512KB
DDR	32/64-bit DDR2/DDR3	32/64-bit DDR2/DDR3
GbE	3 x 10/100/1000	3 x 10/100/1000
PCIe Gen 1.0	3 controllers w/ 4 SERDES	3 controllers w/ 4 SERDES
sRIO 1.2	2 x1 or 1 x4	2 x1 or 1 x4
USB 2.0	1	1
Memory Card	SD/MMC	SD/MMC
Other interfaces	SPI, 2xI²C, DUART	SPI, 2xI²C, DUART
Accelerators	SEC3.1	SEC3.1

Buy/Parametrics

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Design Resources

Design Files

Quick reference to our design files types.

1 design file

Receive the full breakdown. See the product footprint and more in the eCad file.

Models
P2020 BSDL Model

ZIPRev AJan 14, 2013 00:00:0011.5 KBP2020BSDL
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Software

Quick reference to our software types.

3 software files

Development IDEs and Build Tools
CodeWarrior Development Studio v10 for Power Architecture® Technology (Eclipse) EVALFeatured

FLEXERARev 10.5.xNov 26, 2019 11:05:001 KBCWX-PA-PRO-EX

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Configuration Tools
Processor Expert^® Software – Component Development Environment v1.0.4

Download Options
Development IDEs and Build Tools
CodeWarrior^® Development Suites for Networked Applications

Download Options

Note: For better experience, software downloads are recommended on desktop.

Training

1 trainings

On-Demand
Security 101: Introduction to Security Acceleration in QorIQ Processors

4 minEnglish

Account Required

QorIQ® P2020 and P2010 Dual- and Single-Core Communications Processors

Product Details

Block Diagram

Freescale QorIQ P2020/10 Communication Processor Block Diagram

Features

Core Complex

Networking Elements

Accelerators and Memory Control

Basic Peripherals and Interconnect

Additional Features

Comparison Table

Applications

Consumer

Industrial

Buy/Parametrics

Documentation

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Application Note (30)

SEC 2/3x Descriptor Programmer’s Guide[AN3645]

AN5125, Introduction to Device Trees - Application Note[AN5125]

AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note[AN4039]

AN4261, P2020 QorIQ Integrated Processor Design Checklist - Application Note[AN4261]

AN4309, P2010 QorIQ Integrated Processor Design Checklist - Application Note[AN4309]

AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes[AN4848]

AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes[AN4531]

AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note[AN3940]

QorIQ eSPI Controller Register Setting Considerations and Programming Examples[AN4375]

Booting from On-Chip ROM (eSDHC or eSPI)[AN3659]

Verification of the IEEE 1588 Interface[AN4326]

SerDes Reference Clock Interfacing and HSSI Measurements Recommendations[AN4311]

Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors[AN3423]

DDR Interleaving for PowerQUICC and QorIQ Processors[AN3939]

AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes[AN4064]

Understanding SYSCLK Jitter[AN4056]

The SystemID Format for Power Architecture™ Development Systems[AN3638]

Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx[AN3646]

MPC603e and e500 Register Model Comparison[AN2490]

Implementing SGMII Interfaces on the PowerQUICC™ III[AN3869]

Determining the I2C Frequency Divider Ratio for SCL[AN2919]

AN3542, SMP Boot Process for Dual E500 Cores - Application Notes[AN3542]

PowerQUICC™ Data Cache Coherency[AN3544]

Coherency and Synchronization Requirements for PowerQUICC™ III[AN3441]

Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC)[AN3537]

Error Correction and Error Handling on PowerQUICC (TM) III Processors[AN3532]

AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes[AN3445]

AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes[AN3531]

Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces[AN2910]

AN2665, e500 Software Optimization Guide (eSOG) - Application Notes[AN2665]

Application Note Software (1)

Challenges in Testing for Power Rail Shorts with New Technologies[AN3372]

Brochure (1)

QorIQ P2 Family Communications Processors - Application Brief[P2_FAMILY_APP_BRO]

Data Sheet (2)

P2010 QorIQ Integrated Processor Hardware Specifications - Data Sheets[P2010EC]

P2020 QorIQ Integrated Processor Hardware Specifications - Data Sheets[P2020EC]

Fact Sheet (5)

QorIQ™ P2020 UTM/Security Appliance Solution[P2020UTMAPPFS]

Modular AdvancedMC Platform for Broadband/LTE Base Stations Fact Sheet[LTEWIMAXFS]

P2020 Development System[P2020DS]

P2020 Reference Design Board[P2020RDB]

Fact Sheet[QP20XXFS]Featured

Product Brief (1)

P2020/P2010 QorIQ Communications Processor Product Brief[P2020PB]

Reference Manual (5)

EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual[EREF_RM]

P2020 Security (SEC 3.1) Reference Manual[P2020SECRM]

Embedded Multicore: An Introduction[EMBMCRM]

PowerPC ™ e500 Core Family - Reference Manual[E500CORERM]

P2020 QorIQ Integrated Processor Reference Manual[P2020RM]Featured

Supporting Information (2)

FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP® Cryptographic Accelerators - White Paper[FSLNISTCAVP]

P2020 Family Customer Export Control Information[P2020FAMPECI]

Technical Notes (1)

COM Express Pin Assignments for QorIQ Devices[EB739]

User Guide (1)

Spectre and Meltdown Updates for Power ISA Cores[SPECTRE-MELTDOWN-POWER-ISA-DOC]

White Paper (3)

Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper[SPECTREPPCWP]

Tuning QorIQ Processor Performance[LTEWHTPPRCRTBLA4]

Understanding Cryptographic Performance[CRYPTOWP]

QorIQ^® P2020 and P2010 Dual- and Single-Core Communications Processors

FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP^® Cryptographic Accelerators - White Paper[FSLNISTCAVP]