QorIQ® P1024/15 Single- and Dual-Core Communications Processors

  • This page contains information on a product that is not recommended for new designs.

Block Diagram

Freescale QorIQ P1024/15 Communication Processor Block Diagram

QorIQ<sup>&#174;</sup> P1024/15 Communication Processor Block Diagram

Features

Core Complex

  • Dual (P1024) or single (P1015) high-performance Power Architecture® e500 cores, 32 KB L1 cache, up to 667 MHz
  • 256 KB L2 cache with ECC, also configurable as SRAM and stashing memory

Networking Elements

  • Three 10/100/1000 Mbps enhanced triple speed Ethernet controllers (eTSEC)
  • Two SGMII interfaces
  • Support for IEEE® 1588

Accelerators and Memory Control

  • DDR3 32-bit memory controller with ECC support
  • Integrated security engine
    • Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi
    • XOR acceleration

Basic Peripherals and Interconnect

  • Four lane SERDES up to 3.125 GHz multiplexed across controllers
  • Two PCI Express® Gen1.0 interface controllers
  • Two USB2.0 controllers
  • Enhanced Local Bus Controller (eLBC)
  • TDM
  • eSDHC
  • Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

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Documentation

Quick reference to our documentation types.

1-10 of 39 documents

Compact List

Application Note (25)
Application Note Software (1)
Data Sheet (2)
Fact Sheet (1)
Reference Manual (3)
Supporting Information (3)
Technical Notes (2)
User Guide (1)
White Paper (1)

Design Files

Software

Quick reference to our software types.

3 software files

Note: For better experience, software downloads are recommended on desktop.

Training

1 trainings

Support

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