Layerscape® 1012A Low Power Processor

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Block Diagram

LS1012A Block Diagram

LS1012A Block Diagram

Features

Core Complex

  • Single 600 MHz or 1GHz Arm® Cortex®-A53 core
  • 32 KB-I and 32 KB-D ECC protected cache
  • 256 KB L2 ECC protected cache
  • Over 4000 Coremarks performance

Networking Elements

  • Three-lane SerDes up to 6 GHz multiplexed across controllers supporting
    • One PCI Express® Gen 2 interface
    • One SATA 3.0 Interface
    • Two 1Gb or 2.5Gb Ethernet Controllers

Accelerators and Memory Controllers

  • Packet Forwarding Engine
  • Integrated security engine (SEC)
  • 16-bit DDR3L Memory Controller
  • QuadSPI Flash Memory Interface

Basic Peripherals and Interconnect

  • 1x USB 3.0 + PHY
  • 1x USB 2.0 + ULPI
  • 1x SPI, 2x I2C
  • 2x SD3.0 / SDIO / eMMC
  • 2x UART
  • 5x I2S

Additional Features

  • QorIQ® Trust Architecture
  • Arm TrustZone
  • 9.6 x 9.6mm L-BGA package

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Documentation

Quick reference to our documentation types.

1-10 of 27 documents

Compact List

Application Note (18)
Data Sheet (1)
Errata (1)
Fact Sheet (1)
Product Brief (1)
Reference Manual (2)
Supporting Information (3)

Design Files

Hardware

Quick reference to our board types.

5 hardware offerings

Software

Quick reference to our software types.

1-5 of 7 software files

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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 15 engineering services

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To find additional partner offerings that support this product, visit our Partner Marketplace.

Training

4 trainings

Support

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