PowerQUICC® Processor with CPM (1 SCC, 2 SMC), 10/100 Ethernet

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Block Diagram

MPC855T_BLKDIAG

Features

  • 4-Kbyte Instruction Cache
  • 4-Kbyte Data Cache
  • 8 Kb Dual Port RAM
  • Instruction and Data MMUs
  • Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8, 16, and 32 Bits)
  • 32 Address Lines
  • Complete Static Design (0-80 MHz Operation)
  • Memory Controller (Eight Banks)
  • General-Purpose Timers
  • System Integration Unit (SIU)
  • Interrupts
  • Communications Processor Module (CPM)
  • Four Baud Rate Generators
  • One SCC (Serial Communication Controller)
  • Two SMCs (Serial Management Channels)
  • One SPI (Serial Peripheral Interface)
  • One I²C (Inter-Integrated Circuit) Port
  • Time-Slot Assigner
  • Parallel Interface Port
  • PCMCIA Interface
  • Low Power Support
  • Debug Interface
  • 3.3 V Operation with 3.3V I/O

Comparison Table

MPC855T Versions and Masks

Qual Process Mask IMMR [16:31]
Rev D.4 XC .32µ TLM 3K20A 0x0502
Rev D.3 XC .32µ TLM 2K20A 0x0501

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Documentation

Quick reference to our documentation types.

1-10 of 38 documents

Compact List

Application Note (17)
Application Note Software (6)
Data Sheet (1)
Errata (1)
Fact Sheet (1)
Package Information (2)
Product Brief (1)
Product Change Notice (1)
Reference Manual (5)
Selector Guide (3)

Design Files

Hardware

Quick reference to our board types.

3 hardware offerings

Software

Quick reference to our software types.

1 software file

Note: For better experience, software downloads are recommended on desktop.

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