Low-Power PowerQUICC® II Pro Processor with DDR2, eSDHC, PCI Express, eTSEC, USB, IEEE® 1588

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Block Diagram

NXP PowerQUIICC MPC8308 Communications Processor Block Diagram

NXP<sup>&#174;</sup> PowerQUIICC MPC8308 Communications Processor Block Diagram

Features

  • e300c3 core built on Power Architecture® technology, up to 400 MHz
  • 16 KB instruction/16 KB data cache
  • DDR2 memory controller, 266 MHz data rate
  • Local bus controller
  • 1 x PCI Express interface
  • 2 x 10/100/1000 MACs, MII, RGMII
  • USB 2.0 host/device
  • eSDHC
  • DUART
  • 2 x I²C
  • Serial peripheral interface
  • IEEE 1588v2 time synchronization
  • < 1.23W at 333 MHz (typical)
  • 473-pin MAPBGA package, 19 mm x 19 mm
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

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Documentation

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1-10 of 14 documents

Compact List

Application Note (7)
Data Sheet (1)
Errata (1)
Fact Sheet (2)
Product Brief (1)
Reference Manual (1)
White Paper (1)

Design Files

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2 design files

Hardware

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3 hardware offerings

Software

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2 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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Training

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