32-Bit Arm® Cortex®-M3 Flashless MCU with Security Features; 136 KB SRAM; EMC

See product image

Product Details

Features

  • Processor core
    • Arm Cortex-M3 processor, running at frequencies of up to 180 MHz.
    • Arm Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
    • Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
    • Non-maskable Interrupt (NMI) input.
    • JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
    • Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
    • System tick timer.
  • On-chip memory
    • 136 kB SRAM for code and data use.
    • Multiple SRAM blocks with separate bus access.
    • 64 kB ROM containing boot code and on-chip software drivers.
    • 64 bit One-Time Programmable (OTP) memory for general-purpose use.
    • Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key storage One bank can store an encrypted key for decoding the boot image.
  • AES engine for encryption and decryption of the boot image and data with DMA support and programmable via a ROM-based API.
  • Clock generation unit
    • Crystal oscillator with an operating range of 1 MHz to 25 MHz.
    • 12 MHz internal RC oscillator trimmed to 1.5 % accuracy over temperature and voltage.
    • Ultra-low power RTC crystal oscillator.
    • Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.
    • Clock output.
  • Configurable digital peripherals:
    • State Configurable Timer (SCTimer/PWM) subsystem on AHB.
    • Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like timers, SCTimer/PWM, and ADC0/1.
  • Serial interfaces
    • Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.
    • Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification.
    • Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge.
    • Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.
    • One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.
    • One standard I²C-bus interface with monitor mode and standard I/O pins.
    • Two I²S interfaces with DMA support, each with one input and one output.
  • Digital peripherals
    • External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.
    • Secure Digital Input Output (SD/MMC) card interface.
    • Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB followers
    • Up to 83 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.
    • GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
    • Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.
    • Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
    • Four general-purpose timer/counters with capture and match capabilities.
    • One motor control PWM for three-phase motor control.
    • Repetitive Interrupt timer (RI timer).
    • Windowed watchdog timer.
    • Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
    • Alarm timer; can be battery powered.
  • Analog peripherals
    • One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
    • Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC.
  • Unique ID for each device.
  • Power
    • Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain.
    • RTC power domain can be powered separately by a 3 V battery supply.
    • Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
    • Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.
    • Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.
    • Brownout detect with four separate thresholds for interrupt and forced reset.
    • Power-On Reset (POR).
  • Available as LQFP144 package.

Target Applications

  • Communication hubs
  • Automotive aftermarket
  • Power management
  • Consumer health devices
  • Embedded audio applications
  • Industrial control
  • Industrial automation
  • White goods

Buy/Parametrics










































































































Documentation

Quick reference to our documentation types.

1-10 of 20 documents

Compact List

Application Note (12)
Brochure (1)
Data Sheet (1)
Errata (1)
Fact Sheet (1)
Package Information (1)
Supporting Information (1)
Training Presentation (1)
User Guide (1)

Design Files

Quick reference to our design files types.

2 design files

Hardware

Quick reference to our board types.

1-5 of 6 hardware offerings

Show All

Software

Quick reference to our software types.

5 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

3 engineering services

To find additional partner offerings that support this product, visit our Partner Marketplace.

Training

9 trainings

Show All

Support