Kinetis® K28-150 MHz, 2x USB, Core Voltage Bypass, 2MB Flash, 1MB SRAM MCUs based on Arm® Cortex®-M4

Block Diagram

Kinetis K27/K28 USB MCUs Block Diagram

Kinetis K27/K28 USB MCUs Block Diagram

Features

Performance

  • 150 MHz (max) Cortex-M4 with DSP instructions and Single Precision Floating Point unit (FPU)
  • 32-channel DMA with asynchronous support in Stop mode
  • Crossbar switch enables concurrent multi-leader bus accesses, increasing bus bandwidth

Ultra-Low-Power

  • Active run power core consumption @120Mhz: <258 µA/MH (TYP) (@25C) running from internal flash
  • Static power consumption down to <14µA with full 1MB SRAM retention and <6 µS wakeup
  • Lowest static mode down to 254 nA (VLLS0)

Memory

  • 2 MB dual bank embedded program flash
  • 1 MB of SRAM
  • 8 KB I/D Cache + 8 KB System Cache
  • 32-bit SDRAM controller
  • QuadSPI interface with eXecution-In-Place (XiP)

Mixed-Signal Capability

  • 16-bit SAR ADC: Up to 18ch Single-Ended / 3ch Differential
  • 12-bit DAC
  • Two analog comparators (CMP) containing a 6-bit DAC and programmable reference input
  • 1.2V Analog voltage reference

Timing and Control

  • One 4 ch-Periodic interrupt timer
  • Two 16-bit low-power timer PWM modules
  • Two 8-ch motor control/general purpose/PWM timers
  • Two 2-ch quadrature decoder/general purpose timers
  • Real-time clock with independent 3.6 V power domain
  • Programmable delay block

Human-Machine Interface (HMI)

  • 32-ch Programmable module (FlexIO) to emulate various serial, parallel or custom interfaces

Connectivity and Communications

  • Dual USB Controllers: High-Speed (HS) w/ integrated HS PHY + crystal-less Full-Speed (FS) operations
  • Five Low Power UART (LPUART) modules
  • Two I2S modules for audio system interfacing and four I2C modules
  • Four SPI modules (One supports up to 40 Mbps)
  • 32-ch Programmable module (FlexIO) to emulate various serial, parallel or custom interfaces
  • Secure Digital Host Controller (SDHC)

Reliability, Safety and Security

  • Cyclic redundancy check (CRC) engine validates memory contents and communication data, increasing system reliability
  • True random number generator (TRNG)
  • Memory Mapped Crypto Acceleration Unit (MMCAU): 256-bit DES, AES, SHA accelerator

Comparison Table

Kinetis MCU sub-family Part # Mask Set Flash SRAM PMC w/ Core Voltage BypassPackages Development board
K28 MK28FN2M0ACAU15R 3N96T
(recommended)
2 MB 1 MB Yes210 WLCSPFRDM-K28F
MK28FN2M0AVMI15 169 MAPBGA
MK28FN2M0CAU15R 2N96T 210 WLCSP
MK28FN2M0VMI15 169 MAPBGA
K27 MK27FN2M0AVMI15 3N96T
(recommended)
No 169 MABPGA
MK27FN2M0VMI15 2N96T

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Documentation

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Compact List

Application Note (42)
Application Note Software (1)
Data Sheet (2)
Errata (2)
Fact Sheet (1)
Quick Reference Guide (1)
Reference Manual (1)
Selector Guide (1)
User Guide (8)
White Paper (1)

Design Files

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2 design files

Hardware

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Software

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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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Training

5 trainings