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Derivative.h

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00001 
00016 #ifndef _DERIVATIVE_H_
00017  #define _DERIVATIVE_H_
00018 
00019 #include "MPC551x.h"
00021 #include "typedefs.h"
00022 
00023 /*------------------------------- MPC551x Registers ---------------------------*/
00024 
00025 /*----------------------- PORT REGISTERS -------------------*/
00026 /* All MCU mapped registers available within this file violates MISRA 2004 rule 11.3 because addressing memory mapped registers */
00027 #define SIU_PCR(PCR_OFFSET)    SIU.PCR[PCR_OFFSET].R
00028 #define SIU_GPDO(GPDO_OFFSET)  SIU.GPDO[GPDO_OFFSET].R
00029 /*----------------------- PIT REGISTERS  -------------------*/
00030 #define PIT_TLVAL0             PIT.TLVAL0.R  
00031 #define PIT_TLVAL1             PIT.TLVAL1.R  
00032 #define PIT_TLVAL2                     PIT.TLVAL2.R  
00033 #define PIT_TLVAL3                         PIT.TLVAL3.R  
00034 #define PIT_TLVAL4                         PIT.TLVAL4.R  
00035 #define PIT_TLVAL5                         PIT.TLVAL5.R
00036 #define PIT_TLVAL6                     PIT.TLVAL6.R
00037 #define PIT_TLVAL7                         PIT.TLVAL7.R
00038 #define PIT_EN                 PIT.EN.R
00039 #define PIT_CTRL               PIT.CTRL.R
00040 #define PIT_FLG                PIT.FLG.R
00041 #define PIT_INTEN              PIT.INTEN.R 
00042 #define PIT_INTSEL             PIT.INTSEL.R
00043 #define PIT_FLG_TIF1           PIT.FLG.B.TIF1
00044 
00045 /*----------------------- INTC REGISTERS  -------------------*/
00047 #define INT_PSR(u8InterruptNum, u8Priority)   (INTC.PSR[u8InterruptNum].R = (uint8_t)u8Priority)
00048 #define INTC_HVEN_PRC0        INTC.MCR.B.HVEN_PRC0
00049 #define INTC_HVEN_PRC1        INTC.MCR.B.HVEN_PRC1
00050 #define INTC_CPR_PRC0_PRI     INTC.CPR_PRC0.B.PRI
00051 #define INTC_CPR_PRC1_PRI     INTC.CPR_PRC1.B.PRI
00052 
00053 /*---------------------- SIU REGISTERS ----------------------*/
00054 #define SIU_ECCR_EBDF        SIU.ECCR.B.EBDF
00055 #define SIU_SYSCLK_SYSCLKSEL SIU.SYSCLK.B.SYSCLKSEL    
00056 
00057 /*---------------------- CRP REGISTERS ----------------------*/
00058 #define CRP_CLKSRC_XOSCEN    CRP.CLKSRC.B.XOSCEN
00059 
00060 /*---------------------- FLL REGISTERS ----------------------*/
00061 #define FMPLL_ESYNCR1        FMPLL.ESYNCR1.R  
00062 #define FMPLL_ESYNCR2        FMPLL.ESYNCR2.R  
00063 #define FMPLL_SYNSR_LOCK     FMPLL.SYNSR.B.LOCK    
00064  
00065  
00066 #endif