Freescale Semiconductor Inc.
    Regional Technical Application Center

 

Main Page | Class List | Directories | File List | File Members | Related Pages

MPC551x.h

00001 /**************************************************************************/
00002 /* FILE NAME: mpc5516.h                      COPYRIGHT (c) Freescale 2007 */
00003 /* VERSION:  1.2                                  All Rights Reserved     */
00004 /*                                                                        */
00005 /* DESCRIPTION:                                                           */
00006 /* This file contain all of the register and bit field definitions for    */
00007 /* MPC5516.                                                               */
00008 /**************************************************************************/
00009 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
00010 
00011 /*************************************************/
00012 /* Example instantiation and use:                */
00013 /*                                               */
00014 /*  <MODULE>.<REGISTER>.B.<BIT> = 1;             */
00015 /*  <MODULE>.<REGISTER>.R       = 0x10000000;    */
00016 /*                                               */
00017 /*************************************************/
00018 
00019 #ifndef _MPC5516_H_
00020 #define _MPC5516_H_
00021 
00022 #include "typedefs.h"
00023 
00024 #ifdef  __cplusplus
00025 extern "C" {
00026 #endif
00027 
00028 #ifdef __MWERKS__
00029 #pragma push
00030 #pragma ANSI_strict off
00031 #endif
00032 
00033 /****************************************************************************/
00034 /*                     MODULE : CRP                                         */
00035 /****************************************************************************/
00036     struct CRP_tag {
00037 
00038         union {
00039             vuint32_t R;
00040             struct {
00041                 vuint32_t:12;
00042                 vuint32_t KIRCEN:1;
00043                 vuint32_t XOSCEN:1;
00044                   vuint32_t:1;
00045                 vuint32_t KOSCEN:1;
00046                 vuint32_t TRIM32IRC:8;
00047                 vuint32_t TRIMIRC:8;
00048             } B;
00049         } CLKSRC;               //Clock Source Register
00050 
00051         uint32_t crp_reserved1[3];
00052 
00053         union {
00054             vuint32_t R;
00055             struct {
00056                 vuint32_t CNTEN:1;
00057                 vuint32_t RTCIE:1;
00058                 vuint32_t RTCF:1;
00059                 vuint32_t ROVREN:1;
00060                 vuint32_t RTCVAL:12;
00061                 vuint32_t APIEN:1;
00062                 vuint32_t APIIE:1;
00063                 vuint32_t APIF:1;
00064                 vuint32_t CLKSEL:2;
00065                 vuint32_t ROVRF:1;
00066                 vuint32_t APIVAL:10;
00067             } B;
00068         } RTCSC;                //RTC Status and Control Register
00069 
00070         union {
00071             vuint32_t R;
00072             struct {
00073                 vuint32_t:5;
00074                 vuint32_t RTCCNT:27;
00075             } B;
00076         } RTCCNT;               //RTC Counter Register
00077 
00078         uint32_t crp_reserved2[10];
00079 
00080         union {
00081             vuint32_t R;
00082             struct {
00083                 vuint32_t WKPSEL7:4;
00084                 vuint32_t WKPSEL6:4;
00085                 vuint32_t WKPSEL5:4;
00086                 vuint32_t WKPSEL4:4;
00087                 vuint32_t WKPSEL3:4;
00088                 vuint32_t WKPSEL2:4;
00089                 vuint32_t WKPSEL1:4;
00090                 vuint32_t WKPSEL0:4;
00091             } B;
00092         } WKPINSEL;             //Wakeup Pin Source Select Register
00093 
00094         union {
00095             vuint32_t R;
00096             struct {
00097                 vuint32_t WKPDET7:2;
00098                 vuint32_t WKPDET6:2;
00099                 vuint32_t WKPDET5:2;
00100                 vuint32_t WKPDET4:2;
00101                 vuint32_t WKPDET3:2;
00102                 vuint32_t WKPDET2:2;
00103                 vuint32_t WKPDET1:2;
00104                 vuint32_t WKPDET0:2;
00105                   vuint32_t:5;
00106                 vuint32_t RTCOVREN:1;
00107                 vuint32_t RTCWKEN:1;
00108                 vuint32_t APIWKEN:1;
00109                   vuint32_t:7;
00110                 vuint32_t WKCLKSEL:1;
00111             } B;
00112         } WKE;                  //Wakeup Source Enable Register
00113 
00114         uint32_t crp_reserved3[2];
00115 
00116         union {
00117             vuint32_t R;
00118             struct {
00119                 vuint32_t Z1VEC:30;
00120                 vuint32_t Z1RST:1;
00121                 vuint32_t VLE:1;
00122             } B;
00123         } Z1VEC;                //Z1 Reset Vector Register
00124 
00125         union {
00126             vuint32_t R;
00127             struct {
00128                 vuint32_t Z0VEC:30;
00129                 vuint32_t Z0RST:1;
00130                   vuint32_t:1;
00131             } B;
00132         } Z0VEC;                //Z0 Reset Vector Register
00133 
00134         union {
00135             vuint32_t R;
00136             struct {
00137                 vuint32_t RECPTR:30;
00138                 vuint32_t FASTREC:1;
00139                   vuint32_t:1;
00140             } B;
00141         } RECPRTR;              //Reset Recovery Pointer Register
00142 
00143         uint32_t crp_reserved4;
00144 
00145         union {
00146             vuint32_t R;
00147             struct {
00148                 vuint32_t SLEEPF:1;
00149                 vuint32_t STOPF:1;
00150                   vuint32_t:3;
00151                 vuint32_t WKRLLOVRF:1;
00152                 vuint32_t WKAPIF:1;
00153                 vuint32_t WKRTCF:1;
00154                 vuint32_t PWKSCRF:8;
00155                 vuint32_t SLEEP:1;
00156                 vuint32_t STOP:1;
00157                   vuint32_t:1;
00158                 vuint32_t PKREL:1;
00159                 vuint32_t STOP12EN:1;
00160                 vuint32_t RAMSEL:3;
00161                 vuint32_t PWKSRIE:8;
00162             } B;
00163         } PSCR;                 //Power Status and Control Register
00164 
00165         uint32_t crp_reserved5[3];
00166 
00167         union {
00168             vuint32_t R;
00169             struct {
00170                 vuint32_t LVI5IE:1;
00171                 vuint32_t LVI5HIE:1;
00172                 vuint32_t LVI5F:1;
00173                 vuint32_t LVI5HF:1;
00174                 vuint32_t LVILOCK:1;
00175                 vuint32_t LVI5RE:1;
00176                   vuint32_t:26;
00177             } B;
00178         } LVISC;                //LVI Status and Control Register
00179 
00180     };
00181 /****************************************************************************/
00182 /*                          MODULE : DMAMUX                                 */
00183 /****************************************************************************/
00184     struct DMAMUX_tag {
00185         union {
00186             vuint8_t R;
00187             struct {
00188                 vuint8_t ENBL:1;
00189                 vuint8_t TRIG:1;
00190                 vuint8_t SOURCE:6;
00191             } B;
00192         } CHCONFIG[16];         /* DMA Channel Configuration Register */
00193 
00194     };
00195 /****************************************************************************/
00196 /*                          MODULE : DSPI                                   */
00197 /****************************************************************************/
00198     struct DSPI_tag {
00199         union {
00200             vuint32_t R;
00201             struct {
00202                 vuint32_t MSTR:1;
00203                 vuint32_t CONT_SCKE:1;
00204                 vuint32_t DCONF:2;
00205                 vuint32_t FRZ:1;
00206                 vuint32_t MTFE:1;
00207                 vuint32_t PCSSE:1;
00208                 vuint32_t ROOE:1;
00209                   vuint32_t:2;
00210                 vuint32_t PCSIS5:1;
00211                 vuint32_t PCSIS4:1;
00212                 vuint32_t PCSIS3:1;
00213                 vuint32_t PCSIS2:1;
00214                 vuint32_t PCSIS1:1;
00215                 vuint32_t PCSIS0:1;
00216                 vuint32_t DOZE:1;
00217                 vuint32_t MDIS:1;
00218                 vuint32_t DIS_TXF:1;
00219                 vuint32_t DIS_RXF:1;
00220                 vuint32_t CLR_TXF:1;
00221                 vuint32_t CLR_RXF:1;
00222                 vuint32_t SMPL_PT:2;
00223                   vuint32_t:7;
00224                 vuint32_t HALT:1;
00225             } B;
00226         } MCR;                  /* Module Configuration Register */
00227 
00228         uint32_t dspi_reserved1;
00229 
00230         union {
00231             vuint32_t R;
00232             struct {
00233                 vuint32_t TCNT:16;
00234                   vuint32_t:16;
00235             } B;
00236         } TCR;
00237 
00238         union {
00239             vuint32_t R;
00240             struct {
00241                 vuint32_t DBR:1;
00242                 vuint32_t FMSZ:4;
00243                 vuint32_t CPOL:1;
00244                 vuint32_t CPHA:1;
00245                 vuint32_t LSBFE:1;
00246                 vuint32_t PCSSCK:2;
00247                 vuint32_t PASC:2;
00248                 vuint32_t PDT:2;
00249                 vuint32_t PBR:2;
00250                 vuint32_t CSSCK:4;
00251                 vuint32_t ASC:4;
00252                 vuint32_t DT:4;
00253                 vuint32_t BR:4;
00254             } B;
00255         } CTAR[8];              /* Clock and Transfer Attributes Registers */
00256 
00257         union {
00258             vuint32_t R;
00259             struct {
00260                 vuint32_t TCF:1;
00261                 vuint32_t TXRXS:1;
00262                   vuint32_t:1;
00263                 vuint32_t EOQF:1;
00264                 vuint32_t TFUF:1;
00265                   vuint32_t:1;
00266                 vuint32_t TFFF:1;
00267                   vuint32_t:5;
00268                 vuint32_t RFOF:1;
00269                   vuint32_t:1;
00270                 vuint32_t RFDF:1;
00271                   vuint32_t:1;
00272                 vuint32_t TXCTR:4;
00273                 vuint32_t TXNXTPTR:4;
00274                 vuint32_t RXCTR:4;
00275                 vuint32_t POPNXTPTR:4;
00276             } B;
00277         } SR;                   /* Status Register */
00278 
00279         union {
00280             vuint32_t R;
00281             struct {
00282                 vuint32_t TCFRE:1;
00283                   vuint32_t:2;
00284                 vuint32_t EOQFRE:1;
00285                 vuint32_t TFUFRE:1;
00286                   vuint32_t:1;
00287                 vuint32_t TFFFRE:1;
00288                 vuint32_t TFFFDIRS:1;
00289                   vuint32_t:4;
00290                 vuint32_t RFOFRE:1;
00291                   vuint32_t:1;
00292                 vuint32_t RFDFRE:1;
00293                 vuint32_t RFDFDIRS:1;
00294                   vuint32_t:16;
00295             } B;
00296         } RSER;                 /* DMA/Interrupt Request Select and Enable Register */
00297 
00298         union {
00299             vuint32_t R;
00300             struct {
00301                 vuint32_t CONT:1;
00302                 vuint32_t CTAS:3;
00303                 vuint32_t EOQ:1;
00304                 vuint32_t CTCNT:1;
00305                   vuint32_t:4;
00306                 vuint32_t PCS5:1;
00307                 vuint32_t PCS4:1;
00308                 vuint32_t PCS3:1;
00309                 vuint32_t PCS2:1;
00310                 vuint32_t PCS1:1;
00311                 vuint32_t PCS0:1;
00312                 vuint32_t TXDATA:16;
00313             } B;
00314         } PUSHR;                /* PUSH TX FIFO Register */
00315 
00316         union {
00317             vuint32_t R;
00318             struct {
00319                 vuint32_t:16;
00320                 vuint32_t RXDATA:16;
00321             } B;
00322         } POPR;                 /* POP RX FIFO Register */
00323 
00324         union {
00325             vuint32_t R;
00326             struct {
00327                 vuint32_t TXCMD:16;
00328                 vuint32_t TXDATA:16;
00329             } B;
00330         } TXFR[4];              /* Transmit FIFO Registers */
00331 
00332         vuint32_t DSPI_reserved_txf[12];
00333 
00334         union {
00335             vuint32_t R;
00336             struct {
00337                 vuint32_t:16;
00338                 vuint32_t RXDATA:16;
00339             } B;
00340         } RXFR[4];              /* Transmit FIFO Registers */
00341 
00342         vuint32_t DSPI_reserved_rxf[12];
00343 
00344         union {
00345             vuint32_t R;
00346             struct {
00347                 vuint32_t MTOE:1;
00348                   vuint32_t:1;
00349                 vuint32_t MTOCNT:6;
00350                   vuint32_t:4;
00351                 vuint32_t TXSS:1;
00352                 vuint32_t TPOL:1;
00353                 vuint32_t TRRE:1;
00354                 vuint32_t CID:1;
00355                 vuint32_t DCONT:1;
00356                 vuint32_t DSICTAS:3;
00357                   vuint32_t:6;
00358                 vuint32_t DPCS5:1;
00359                 vuint32_t DPCS4:1;
00360                 vuint32_t DPCS3:1;
00361                 vuint32_t DPCS2:1;
00362                 vuint32_t DPCS1:1;
00363                 vuint32_t DPCS0:1;
00364             } B;
00365         } DSICR;                /* DSI Configuration Register */
00366 
00367         union {
00368             vuint32_t R;
00369             struct {
00370                 vuint32_t:16;
00371                 vuint32_t SER_DATA:16;
00372             } B;
00373         } SDR;                  /* DSI Serialization Data Register */
00374 
00375         union {
00376             vuint32_t R;
00377             struct {
00378                 vuint32_t:16;
00379                 vuint32_t ASER_DATA:16;
00380             } B;
00381         } ASDR;                 /* DSI Alternate Serialization Data Register */
00382 
00383         union {
00384             vuint32_t R;
00385             struct {
00386                 vuint32_t:16;
00387                 vuint32_t COMP_DATA:16;
00388             } B;
00389         } COMPR;                /* DSI Transmit Comparison Register */
00390 
00391         union {
00392             vuint32_t R;
00393             struct {
00394                 vuint32_t:16;
00395                 vuint32_t DESER_DATA:16;
00396             } B;
00397         } DDR;                  /* DSI deserialization Data Register */
00398 
00399     };
00400 /****************************************************************************/
00401 /*                     MODULE : External Bus Interface (EBI)                */
00402 /****************************************************************************/
00403 
00404 /* CS_tag instantiated within EBI_tag */
00405     struct CS_tag {
00406         union {                 /* Base Register Bank */
00407             vuint32_t R;
00408             struct {
00409                 vuint32_t BA:17;
00410                   vuint32_t:3;
00411                 vuint32_t PS:1;
00412                   vuint32_t:4;
00413                 vuint32_t BL:1;
00414                 vuint32_t WEBS:1;
00415                 vuint32_t TBDIP:1;
00416                   vuint32_t:2;
00417                 vuint32_t BI:1;
00418                 vuint32_t V:1;
00419             } B;
00420         } BR;
00421 
00422         union {                 /* Option Register Bank */
00423             vuint32_t R;
00424             struct {
00425                 vuint32_t AM:17;
00426                   vuint32_t:7;
00427                 vuint32_t SCY:4;
00428                   vuint32_t:1;
00429                 vuint32_t BSCY:2;
00430                   vuint32_t:1;
00431             } B;
00432         } OR;
00433     };
00434 
00435     struct EBI_tag {
00436         union {                 /* Module Configuration Register */
00437             vuint32_t R;
00438             struct {
00439                 vuint32_t:16;
00440                 vuint32_t ACGE:1;
00441                 vuint32_t EXTM:1;
00442                 vuint32_t EARB:1;
00443                   vuint32_t:6;
00444                 vuint32_t MDIS:1;
00445                   vuint32_t:3;
00446                 vuint32_t D16_31:1;
00447                 vuint32_t AD_MUX:1;
00448                 vuint32_t DBM:1;
00449             } B;
00450         } MCR;
00451 
00452         uint32_t EBI_reserved1;
00453 
00454         union {                 /* Transfer Error Status Register */
00455             vuint32_t R;
00456             struct {
00457                 vuint32_t:30;
00458                 vuint32_t TEAF:1;
00459                 vuint32_t BMTF:1;
00460             } B;
00461         } TESR;
00462 
00463         union {                 /* Bus Monitor Control Register */
00464             vuint32_t R;
00465             struct {
00466                 vuint32_t:16;
00467                 vuint32_t BMT:8;
00468                 vuint32_t BME:1;
00469                   vuint32_t:7;
00470             } B;
00471         } BMCR;
00472 
00473         /* Roll in 2x CS registers */
00474         struct CS_tag CS[2];
00475 
00476     };
00477 /****************************************************************************/
00478 /*                          MODULE : eDMA                                   */
00479 /****************************************************************************/
00480     struct EDMA_tag {
00481         union {
00482             vuint32_t R;
00483             struct {
00484                 vuint32_t:23;
00485                 vuint32_t GRP0PRI:1;
00486                   vuint32_t:4;
00487                 vuint32_t ERGA:1;
00488                 vuint32_t ERCA:1;
00489                 vuint32_t EDBG:1;
00490                   vuint32_t:1;
00491             } B;
00492         } CR;                   /* Control Register */
00493 
00494         union {
00495             vuint32_t R;
00496             struct {
00497                 vuint32_t VLD:1;
00498                   vuint32_t:15;
00499                 vuint32_t GPE:1;
00500                 vuint32_t CPE:1;
00501                 vuint32_t ERRCHN:6;
00502                 vuint32_t SAE:1;
00503                 vuint32_t SOE:1;
00504                 vuint32_t DAE:1;
00505                 vuint32_t DOE:1;
00506                 vuint32_t NCE:1;
00507                 vuint32_t SGE:1;
00508                 vuint32_t SBE:1;
00509                 vuint32_t DBE:1;
00510             } B;
00511         } ESR;                  /* Error Status Register */
00512 
00513         int16_t EDMA_reserved1[3];
00514 
00515         union {
00516             vuint16_t R;
00517             struct {
00518                 vuint16_t ERQ15:1;
00519                 vuint16_t ERQ14:1;
00520                 vuint16_t ERQ13:1;
00521                 vuint16_t ERQ12:1;
00522                 vuint16_t ERQ11:1;
00523                 vuint16_t ERQ10:1;
00524                 vuint16_t ERQ09:1;
00525                 vuint16_t ERQ08:1;
00526                 vuint16_t ERQ07:1;
00527                 vuint16_t ERQ06:1;
00528                 vuint16_t ERQ05:1;
00529                 vuint16_t ERQ04:1;
00530                 vuint16_t ERQ03:1;
00531                 vuint16_t ERQ02:1;
00532                 vuint16_t ERQ01:1;
00533                 vuint16_t ERQ00:1;
00534             } B;
00535         } ERQRL;                /* DMA Enable Request Register Low */
00536 
00537         int16_t EDMA_reserved2[3];
00538 
00539         union {
00540             vuint16_t R;
00541             struct {
00542                 vuint16_t EEI15:1;
00543                 vuint16_t EEI14:1;
00544                 vuint16_t EEI13:1;
00545                 vuint16_t EEI12:1;
00546                 vuint16_t EEI11:1;
00547                 vuint16_t EEI10:1;
00548                 vuint16_t EEI09:1;
00549                 vuint16_t EEI08:1;
00550                 vuint16_t EEI07:1;
00551                 vuint16_t EEI06:1;
00552                 vuint16_t EEI05:1;
00553                 vuint16_t EEI04:1;
00554                 vuint16_t EEI03:1;
00555                 vuint16_t EEI02:1;
00556                 vuint16_t EEI01:1;
00557                 vuint16_t EEI00:1;
00558             } B;
00559         } EEIRL;                /* DMA Enable Error Interrupt Register Low */
00560 
00561         union {
00562             vuint8_t R;
00563             vuint8_t B;
00564         } SERQR;                /* DMA Set Enable Request Register */
00565 
00566         union {
00567             vuint8_t R;
00568             vuint8_t B;
00569         } CERQR;                /* DMA Clear Enable Request Register */
00570 
00571         union {
00572             vuint8_t R;
00573             vuint8_t B;
00574         } SEEIR;                /* DMA Set Enable Error Interrupt Register */
00575 
00576         union {
00577             vuint8_t R;
00578             vuint8_t B;
00579         } CEEIR;                /* DMA Clear Enable Error Interrupt Register */
00580 
00581         union {
00582             vuint8_t R;
00583             vuint8_t B;
00584         } CIRQR;                /* DMA Clear Interrupt Request Register */
00585 
00586         union {
00587             vuint8_t R;
00588             vuint8_t B;
00589         } CER;                  /* DMA Clear error Register */
00590 
00591         union {
00592             vuint8_t R;
00593             vuint8_t B;
00594         } SSBR;                 /* Set Start Bit Register */
00595 
00596         union {
00597             vuint8_t R;
00598             vuint8_t B;
00599         } CDSBR;                /* Clear Done Status Bit Register */
00600 
00601         int16_t EDMA_reserved3[3];
00602 
00603         union {
00604             vuint16_t R;
00605             struct {
00606                 vuint16_t INT15:1;
00607                 vuint16_t INT14:1;
00608                 vuint16_t INT13:1;
00609                 vuint16_t INT12:1;
00610                 vuint16_t INT11:1;
00611                 vuint16_t INT10:1;
00612                 vuint16_t INT09:1;
00613                 vuint16_t INT08:1;
00614                 vuint16_t INT07:1;
00615                 vuint16_t INT06:1;
00616                 vuint16_t INT05:1;
00617                 vuint16_t INT04:1;
00618                 vuint16_t INT03:1;
00619                 vuint16_t INT02:1;
00620                 vuint16_t INT01:1;
00621                 vuint16_t INT00:1;
00622             } B;
00623         } IRQRL;                /* DMA Interrupt Request Low */
00624 
00625         int16_t EDMA_reserved4[3];
00626 
00627         union {
00628             vuint16_t R;
00629             struct {
00630                 vuint16_t ERR15:1;
00631                 vuint16_t ERR14:1;
00632                 vuint16_t ERR13:1;
00633                 vuint16_t ERR12:1;
00634                 vuint16_t ERR11:1;
00635                 vuint16_t ERR10:1;
00636                 vuint16_t ERR09:1;
00637                 vuint16_t ERR08:1;
00638                 vuint16_t ERR07:1;
00639                 vuint16_t ERR06:1;
00640                 vuint16_t ERR05:1;
00641                 vuint16_t ERR04:1;
00642                 vuint16_t ERR03:1;
00643                 vuint16_t ERR02:1;
00644                 vuint16_t ERR01:1;
00645                 vuint16_t ERR00:1;
00646             } B;
00647         } ERL;                  /* DMA Error Low */
00648 
00649         uint32_t edma_reserved1[52];
00650 
00651         union {
00652             vuint8_t R;
00653             struct {
00654                 vuint8_t ECP:1;
00655                   vuint8_t:1;
00656                 vuint8_t GRPPRI:2;
00657                 vuint8_t CHPRI:4;
00658             } B;
00659         } CPR[16];              /* Channel n Priority */
00660 
00661         uint32_t edma_reserved2[956];
00662 
00663 /****************************************************************************/
00664 /*       DMA2 Transfer Control Descriptor                                   */
00665 /****************************************************************************/
00666 
00667         struct tcd_t {          /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */
00668             vuint32_t SADDR;    /* source address */
00669 
00670             vuint16_t SMOD:5;   /* source address modulo */
00671             vuint16_t SSIZE:3;  /* source transfer size */
00672             vuint16_t DMOD:5;   /* destination address modulo */
00673             vuint16_t DSIZE:3;  /* destination transfer size */
00674             vint16_t SOFF;      /* signed source address offset */
00675 
00676             vuint32_t NBYTES;   /* inner (“minor”) byte count */
00677 
00678             vint32_t SLAST;     /* last destination address adjustment, or
00679 
00680                                    scatter/gather address (if e_sg = 1) */
00681             vuint32_t DADDR;    /* destination address */
00682 
00683             vuint16_t CITERE_LINK:1;
00684             vuint16_t CITER:15;
00685 
00686             vint16_t DOFF;      /* signed destination address offset */
00687 
00688             vint32_t DLAST_SGA;
00689 
00690             vuint16_t BITERE_LINK:1;    /* beginning ("major") iteration count */
00691             vuint16_t BITER:15;
00692 
00693             vuint16_t BWC:2;    /* bandwidth control */
00694             vuint16_t MAJORLINKCH:6;    /* enable channel-to-channel link */
00695             vuint16_t DONE:1;   /* channel done */
00696             vuint16_t ACTIVE:1; /* channel active */
00697             vuint16_t MAJORE_LINK:1;    /* enable channel-to-channel link */
00698             vuint16_t E_SG:1;   /* enable scatter/gather descriptor */
00699             vuint16_t D_REQ:1;  /* disable ipd_req when done */
00700             vuint16_t INT_HALF:1;       /* interrupt on citer = (biter >> 1) */
00701             vuint16_t INT_MAJ:1;        /* interrupt on major loop completion */
00702             vuint16_t START:1;  /* explicit channel start */
00703         } TCD[16];              /* transfer_control_descriptor */
00704 
00705     };
00706 
00707     struct EDMA_TCD_alt1_tag {  /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */
00708 
00709         struct tcd_alt1_t {
00710             vuint32_t SADDR;    /* source address */
00711 
00712             vuint16_t SMOD:5;   /* source address modulo */
00713             vuint16_t SSIZE:3;  /* source transfer size */
00714             vuint16_t DMOD:5;   /* destination address modulo */
00715             vuint16_t DSIZE:3;  /* destination transfer size */
00716             vint16_t SOFF;      /* signed source address offset */
00717 
00718             vuint32_t NBYTES;   /* inner (“minor”) byte count */
00719 
00720             vint32_t SLAST;     /* last destination address adjustment, or
00721 
00722                                    scatter/gather address (if e_sg = 1) */
00723             vuint32_t DADDR;    /* destination address */
00724 
00725             vuint16_t CITERE_LINK:1;
00726             vuint16_t CITERLINKCH:6;
00727             vuint16_t CITER:9;
00728 
00729             vint16_t DOFF;      /* signed destination address offset */
00730 
00731             vint32_t DLAST_SGA;
00732 
00733             vuint16_t BITERE_LINK:1;    /* beginning (“major”) iteration count */
00734             vuint16_t BITERLINKCH:6;
00735             vuint16_t BITER:9;
00736 
00737             vuint16_t BWC:2;    /* bandwidth control */
00738             vuint16_t MAJORLINKCH:6;    /* enable channel-to-channel link */
00739             vuint16_t DONE:1;   /* channel done */
00740             vuint16_t ACTIVE:1; /* channel active */
00741             vuint16_t MAJORE_LINK:1;    /* enable channel-to-channel link */
00742             vuint16_t E_SG:1;   /* enable scatter/gather descriptor */
00743             vuint16_t D_REQ:1;  /* disable ipd_req when done */
00744             vuint16_t INT_HALF:1;       /* interrupt on citer = (biter >> 1) */
00745             vuint16_t INT_MAJ:1;        /* interrupt on major loop completion */
00746             vuint16_t START:1;  /* explicit channel start */
00747         } TCD[16];              /* transfer_control_descriptor */
00748 
00749     };
00750 /****************************************************************************/
00751 /*                          MODULE : EMIOS                                  */
00752 /****************************************************************************/
00753     struct EMIOS_tag {
00754         union {
00755             vuint32_t R;
00756             struct {
00757                 vuint32_t DOZEEN:1;
00758                 vuint32_t MDIS:1;
00759                 vuint32_t FRZ:1;
00760                 vuint32_t GTBE:1;
00761                 vuint32_t ETB:1;
00762                 vuint32_t GPREN:1;
00763                   vuint32_t:6;
00764                 vuint32_t SRV:4;
00765                 vuint32_t GPRE:8;
00766                   vuint32_t:8;
00767             } B;
00768         } MCR;                  /* Module Configuration Register */
00769 
00770         union {
00771             vuint32_t R;
00772             struct {
00773                 vuint32_t:8;
00774                 vuint32_t F23:1;
00775                 vuint32_t F22:1;
00776                 vuint32_t F21:1;
00777                 vuint32_t F20:1;
00778                 vuint32_t F19:1;
00779                 vuint32_t F18:1;
00780                 vuint32_t F17:1;
00781                 vuint32_t F16:1;
00782                 vuint32_t F15:1;
00783                 vuint32_t F14:1;
00784                 vuint32_t F13:1;
00785                 vuint32_t F12:1;
00786                 vuint32_t F11:1;
00787                 vuint32_t F10:1;
00788                 vuint32_t F9:1;
00789                 vuint32_t F8:1;
00790                 vuint32_t F7:1;
00791                 vuint32_t F6:1;
00792                 vuint32_t F5:1;
00793                 vuint32_t F4:1;
00794                 vuint32_t F3:1;
00795                 vuint32_t F2:1;
00796                 vuint32_t F1:1;
00797                 vuint32_t F0:1;
00798             } B;
00799         } GFLAG;                /* Global FLAG Register */
00800 
00801         union {
00802             vuint32_t R;
00803             struct {
00804                 vuint32_t:8;
00805                 vuint32_t OU23:1;
00806                 vuint32_t OU22:1;
00807                 vuint32_t OU21:1;
00808                 vuint32_t OU20:1;
00809                 vuint32_t OU19:1;
00810                 vuint32_t OU18:1;
00811                 vuint32_t OU17:1;
00812                 vuint32_t OU16:1;
00813                 vuint32_t OU15:1;
00814                 vuint32_t OU14:1;
00815                 vuint32_t OU13:1;
00816                 vuint32_t OU12:1;
00817                 vuint32_t OU11:1;
00818                 vuint32_t OU10:1;
00819                 vuint32_t OU9:1;
00820                 vuint32_t OU8:1;
00821                 vuint32_t OU7:1;
00822                 vuint32_t OU6:1;
00823                 vuint32_t OU5:1;
00824                 vuint32_t OU4:1;
00825                 vuint32_t OU3:1;
00826                 vuint32_t OU2:1;
00827                 vuint32_t OU1:1;
00828                 vuint32_t OU0:1;
00829             } B;
00830         } OUDIS;                /* Output Update Disable Register */
00831 
00832         union {
00833             vuint32_t R;
00834         } UCDIS;                /* Disable Channel Register */
00835 
00836         uint32_t emios_reserved1[4];
00837 
00838         struct {
00839             union {
00840                 vuint32_t R;    /* Channel A Data Register */
00841             } CADR;
00842 
00843             union {
00844                 vuint32_t R;    /* Channel B Data Register */
00845             } CBDR;
00846 
00847             union {
00848                 vuint32_t R;    /* Channel Counter Register */
00849             } CCNTR;
00850 
00851             union {
00852                 vuint32_t R;
00853                 struct {
00854                     vuint32_t FREN:1;
00855                     vuint32_t ODIS:1;
00856                     vuint32_t ODISSL:2;
00857                     vuint32_t UCPRE:2;
00858                     vuint32_t UCPEN:1;
00859                     vuint32_t DMA:1;
00860                       vuint32_t:1;
00861                     vuint32_t IF:4;
00862                     vuint32_t FCK:1;
00863                     vuint32_t FEN:1;
00864                       vuint32_t:3;
00865                     vuint32_t FORCMA:1;
00866                     vuint32_t FORCMB:1;
00867                       vuint32_t:1;
00868                     vuint32_t BSL:2;
00869                     vuint32_t EDSEL:1;
00870                     vuint32_t EDPOL:1;
00871                     vuint32_t MODE:7;
00872                 } B;
00873             } CCR;              /* Channel Control Register */
00874 
00875             union {
00876                 vuint32_t R;
00877                 struct {
00878                     vuint32_t OVR:1;
00879                       vuint32_t:15;
00880                     vuint32_t OVFL:1;
00881                       vuint32_t:12;
00882                     vuint32_t UCIN:1;
00883                     vuint32_t UCOUT:1;
00884                     vuint32_t FLAG:1;
00885                 } B;
00886             } CSR;              /* Channel Status Register */
00887 
00888             union {
00889                 vuint32_t R;    /* Alternate Channel A Data Register */
00890             } ALTA;
00891 
00892             uint32_t emios_channel_reserved[2];
00893 
00894         } CH[24];
00895 
00896     };
00897 /****************************************************************************/
00898 /*                          MODULE : EQADC                                  */
00899 /****************************************************************************/
00900     struct EQADC_tag {
00901         union {
00902             vuint32_t R;
00903             struct {
00904                 vuint32_t:27;
00905                 vuint32_t ESSIE:2;
00906                   vuint32_t:1;
00907                 vuint32_t DBG:2;
00908             } B;
00909         } MCR;                  /* Module Configuration Register */
00910 
00911         uint32_t eqadc_reserved0;
00912 
00913         union {
00914             vuint32_t R;
00915             struct {
00916                 vuint32_t:6;
00917                 vuint32_t NMF:26;
00918             } B;
00919         } NMSFR;                /* Null Message Send Format Register */
00920 
00921         union {
00922             vuint32_t R;
00923             struct {
00924                 vuint32_t:28;
00925                 vuint32_t DFL:4;
00926             } B;
00927         } ETDFR;                /* External Trigger Digital Filter Register */
00928 
00929         union {
00930             vuint32_t R;
00931             struct {
00932                 vuint32_t CFPUSH:32;
00933             } B;
00934         } CFPR[6];              /* CFIFO Push Registers */
00935 
00936         uint32_t eqadc_reserved1;
00937 
00938         uint32_t eqadc_reserved2;
00939 
00940         union {
00941             vuint32_t R;
00942             struct {
00943                 vuint32_t:16;
00944                 vuint32_t RFPOP:16;
00945             } B;
00946         } RFPR[6];              /* Result FIFO Pop Registers */
00947 
00948         uint32_t eqadc_reserved3;
00949 
00950         uint32_t eqadc_reserved4;
00951 
00952         union {
00953             vuint16_t R;
00954             struct {
00955                 vuint16_t:5;
00956                 vuint16_t SSE:1;
00957                 vuint16_t CFINV:1;
00958                   vuint16_t:1;
00959                 vuint16_t MODE:4;
00960                   vuint16_t:4;
00961             } B;
00962         } CFCR[6];              /* CFIFO Control Registers */
00963 
00964         uint32_t eqadc_reserved5;
00965 
00966         union {
00967             vuint16_t R;
00968             struct {
00969                 vuint16_t NCIE:1;
00970                 vuint16_t TORIE:1;
00971                 vuint16_t PIE:1;
00972                 vuint16_t EOQIE:1;
00973                 vuint16_t CFUIE:1;
00974                   vuint16_t:1;
00975                 vuint16_t CFFE:1;
00976                 vuint16_t CFFS:1;
00977                   vuint16_t:4;
00978                 vuint16_t RFOIE:1;
00979                   vuint16_t:1;
00980                 vuint16_t RFDE:1;
00981                 vuint16_t RFDS:1;
00982             } B;
00983         } IDCR[6];              /* Interrupt and DMA Control Registers */
00984 
00985         uint32_t eqadc_reserved6;
00986 
00987         union {
00988             vuint32_t R;
00989             struct {
00990                 vuint32_t NCF:1;
00991                 vuint32_t TORF:1;
00992                 vuint32_t PF:1;
00993                 vuint32_t EOQF:1;
00994                 vuint32_t CFUF:1;
00995                 vuint32_t SSS:1;
00996                 vuint32_t CFFF:1;
00997                   vuint32_t:5;
00998                 vuint32_t RFOF:1;
00999                   vuint32_t:1;
01000                 vuint32_t RFDF:1;
01001                   vuint32_t:1;
01002                 vuint32_t CFCTR:4;
01003                 vuint32_t TNXTPTR:4;
01004                 vuint32_t RFCTR:4;
01005                 vuint32_t POPNXTPTR:4;
01006             } B;
01007         } FISR[6];              /* FIFO and Interrupt Status Registers */
01008 
01009         uint32_t eqadc_reserved7;
01010 
01011         uint32_t eqadc_reserved8;
01012 
01013         union {
01014             vuint16_t R;
01015             struct {
01016                 vuint16_t:5;
01017                 vuint16_t TCCF:11;
01018             } B;
01019         } CFTCR[6];             /* CFIFO Transfer Counter Registers */
01020 
01021         uint32_t eqadc_reserved9;
01022 
01023         union {
01024             vuint32_t R;
01025             struct {
01026                 vuint32_t CFS0:2;
01027                 vuint32_t CFS1:2;
01028                 vuint32_t CFS2:2;
01029                 vuint32_t CFS3:2;
01030                 vuint32_t CFS4:2;
01031                 vuint32_t CFS5:2;
01032                   vuint32_t:5;
01033                 vuint32_t LCFTCB0:4;
01034                 vuint32_t TC_LCFTCB0:11;
01035             } B;
01036         } CFSSR0;               /* CFIFO Status Register 0 */
01037 
01038         union {
01039             vuint32_t R;
01040             struct {
01041                 vuint32_t CFS0:2;
01042                 vuint32_t CFS1:2;
01043                 vuint32_t CFS2:2;
01044                 vuint32_t CFS3:2;
01045                 vuint32_t CFS4:2;
01046                 vuint32_t CFS5:2;
01047                   vuint32_t:5;
01048                 vuint32_t LCFTCB1:4;
01049                 vuint32_t TC_LCFTCB1:11;
01050             } B;
01051         } CFSSR1;               /* CFIFO Status Register 1 */
01052 
01053         union {
01054             vuint32_t R;
01055             struct {
01056                 vuint32_t CFS0:2;
01057                 vuint32_t CFS1:2;
01058                 vuint32_t CFS2:2;
01059                 vuint32_t CFS3:2;
01060                 vuint32_t CFS4:2;
01061                 vuint32_t CFS5:2;
01062                   vuint32_t:4;
01063                 vuint32_t ECBNI:1;
01064                 vuint32_t LCFTSSI:4;
01065                 vuint32_t TC_LCFTSSI:11;
01066             } B;
01067         } CFSSR2;               /* CFIFO Status Register 2 */
01068 
01069         union {
01070             vuint32_t R;
01071             struct {
01072                 vuint32_t CFS0:2;
01073                 vuint32_t CFS1:2;
01074                 vuint32_t CFS2:2;
01075                 vuint32_t CFS3:2;
01076                 vuint32_t CFS4:2;
01077                 vuint32_t CFS5:2;
01078                   vuint32_t:20;
01079             } B;
01080         } CFSR;
01081 
01082         uint32_t eqadc_reserved11;
01083 
01084         union {
01085             vuint32_t R;
01086             struct {
01087                 vuint32_t:21;
01088                 vuint32_t MDT:3;
01089                   vuint32_t:4;
01090                 vuint32_t BR:4;
01091             } B;
01092         } SSICR;                /* SSI Control Register */
01093 
01094         union {
01095             vuint32_t R;
01096             struct {
01097                 vuint32_t RDV:1;
01098                   vuint32_t:5;
01099                 vuint32_t RDATA:26;
01100             } B;
01101         } SSIRDR;               /* SSI Recieve Data Register */
01102 
01103         uint32_t eqadc_reserved12[17];
01104 
01105         struct {
01106             union {
01107                 vuint32_t R;
01108                 struct {
01109                     vuint32_t:32;
01110                 } B;
01111             } R[4];
01112 
01113             uint32_t eqadc_reserved13[12];
01114 
01115         } CF[6];
01116 
01117         uint32_t eqadc_reserved14[32];
01118 
01119         struct {
01120             union {
01121                 vuint32_t R;
01122                 struct {
01123                     vuint32_t:32;
01124                 } B;
01125             } R[4];
01126 
01127             uint32_t eqadc_reserved15[12];
01128 
01129         } RF[6];
01130 
01131     };
01132 /****************************************************************************/
01133 /*                          MODULE : eSCI                                   */
01134 /****************************************************************************/
01135     struct ESCI_tag {
01136         union {
01137             vuint32_t R;
01138             struct {
01139                 vuint32_t:3;
01140                 vuint32_t SBR:13;
01141                 vuint32_t LOOPS:1;
01142                   vuint32_t:1;
01143                 vuint32_t RSRC:1;
01144                 vuint32_t M:1;
01145                 vuint32_t WAKE:1;
01146                 vuint32_t ILT:1;
01147                 vuint32_t PE:1;
01148                 vuint32_t PT:1;
01149                 vuint32_t TIE:1;
01150                 vuint32_t TCIE:1;
01151                 vuint32_t RIE:1;
01152                 vuint32_t ILIE:1;
01153                 vuint32_t TE:1;
01154                 vuint32_t RE:1;
01155                 vuint32_t RWU:1;
01156                 vuint32_t SBK:1;
01157             } B;
01158         } CR1;                  /* Control Register 1 */
01159 
01160         union {
01161             vuint16_t R;
01162             struct {
01163                 vuint16_t MDIS:1;
01164                 vuint16_t FBR:1;
01165                 vuint16_t BSTP:1;
01166                 vuint16_t IEBERR:1;
01167                 vuint16_t RXDMA:1;
01168                 vuint16_t TXDMA:1;
01169                 vuint16_t BRK13:1;
01170                   vuint16_t:1;
01171                 vuint16_t BESM13:1;
01172                 vuint16_t SBSTP:1;
01173                   vuint16_t:2;
01174                 vuint16_t ORIE:1;
01175                 vuint16_t NFIE:1;
01176                 vuint16_t FEIE:1;
01177                 vuint16_t PFIE:1;
01178             } B;
01179         } CR2;                  /* Control Register 2 */
01180 
01181         union {
01182             vuint16_t R;
01183             struct {
01184                 vuint16_t R8:1;
01185                 vuint16_t T8:1;
01186                   vuint16_t:6;
01187                 vuint8_t D;
01188             } B;
01189         } DR;                   /* Data Register */
01190 
01191         union {
01192             vuint32_t R;
01193             struct {
01194                 vuint32_t TDRE:1;
01195                 vuint32_t TC:1;
01196                 vuint32_t RDRF:1;
01197                 vuint32_t IDLE:1;
01198                 vuint32_t OR:1;
01199                 vuint32_t NF:1;
01200                 vuint32_t FE:1;
01201                 vuint32_t PF:1;
01202                   vuint32_t:3;
01203                 vuint32_t BERR:1;
01204                   vuint32_t:3;
01205                 vuint32_t RAF:1;
01206                 vuint32_t RXRDY:1;
01207                 vuint32_t TXRDY:1;
01208                 vuint32_t LWAKE:1;
01209                 vuint32_t STO:1;
01210                 vuint32_t PBERR:1;
01211                 vuint32_t CERR:1;
01212                 vuint32_t CKERR:1;
01213                 vuint32_t FRC:1;
01214                   vuint32_t:7;
01215                 vuint32_t OVFL:1;
01216             } B;
01217         } SR;                   /* Status Register */
01218 
01219         union {
01220             vuint32_t R;
01221             struct {
01222                 vuint32_t LRES:1;
01223                 vuint32_t WU:1;
01224                 vuint32_t WUD0:1;
01225                 vuint32_t WUD1:1;
01226                 vuint32_t LDBG:1;
01227                 vuint32_t DSF:1;
01228                 vuint32_t PRTY:1;
01229                 vuint32_t LIN:1;
01230                 vuint32_t RXIE:1;
01231                 vuint32_t TXIE:1;
01232                 vuint32_t WUIE:1;
01233                 vuint32_t STIE:1;
01234                 vuint32_t PBIE:1;
01235                 vuint32_t CIE:1;
01236                 vuint32_t CKIE:1;
01237                 vuint32_t FCIE:1;
01238                   vuint32_t:7;
01239                 vuint32_t OFIE:1;
01240                   vuint32_t:8;
01241             } B;
01242         } LCR;                  /* LIN Control Register */
01243 
01244         union {
01245             vuint32_t R;
01246         } LTR;                  /* LIN Transmit Register */
01247 
01248         union {
01249             vuint32_t R;
01250         } LRR;                  /* LIN Recieve Register */
01251 
01252         union {
01253             vuint32_t R;
01254         } LPR;                  /* LIN CRC Polynom Register  */
01255 
01256     };
01257 /****************************************************************************/
01258 /*                     MODULE : FLASH                                       */
01259 /****************************************************************************/
01260     struct FLASH_tag {
01261         union {                 /* Module Configuration Register */
01262             vuint32_t R;
01263             struct {
01264                 vuint32_t:3;
01265                 vuint32_t SFS:1;
01266                 vuint32_t SIZE:4;
01267                   vuint32_t:1;
01268                 vuint32_t LAS:3;
01269                   vuint32_t:3;
01270                 vuint32_t MAS:1;
01271                 vuint32_t EER:1;
01272                 vuint32_t RWE:1;
01273                 vuint32_t BBEPE:1;
01274                 vuint32_t EPE:1;
01275                 vuint32_t PEAS:1;
01276                 vuint32_t DONE:1;
01277                 vuint32_t PEG:1;
01278                   vuint32_t:1;
01279                 vuint32_t PRD:1;
01280                 vuint32_t STOP:1;
01281                   vuint32_t:1;
01282                 vuint32_t PGM:1;
01283                 vuint32_t PSUS:1;
01284                 vuint32_t ERS:1;
01285                 vuint32_t ESUS:1;
01286                 vuint32_t EHV:1;
01287             } B;
01288         } MCR;
01289 
01290         union {                 /* LML Register */
01291             vuint32_t R;
01292             struct {
01293                 vuint32_t LME:1;
01294                   vuint32_t:10;
01295                 vuint32_t SLOCK:1;
01296                   vuint32_t:2;
01297                 vuint32_t MLOCK:2;
01298                   vuint32_t:8;
01299                 vuint32_t LLOCK:8;
01300             } B;
01301         } LMLR;
01302 
01303         union {                 /* HL Register */
01304             vuint32_t R;
01305             struct {
01306                 vuint32_t HBE:1;
01307                   vuint32_t:27;
01308                 vuint32_t HBLOCK:4;
01309             } B;
01310         } HLR;
01311 
01312         union {                 /* SLML Register */
01313             vuint32_t R;
01314             struct {
01315                 vuint32_t SLE:1;
01316                   vuint32_t:10;
01317                 vuint32_t SSLOCK:1;
01318                   vuint32_t:2;
01319                 vuint32_t SMLOCK:2;
01320                   vuint32_t:8;
01321                 vuint32_t SLLOCK:8;
01322             } B;
01323         } SLMLR;
01324 
01325         union {                 /* LMS Register */
01326             vuint32_t R;
01327             struct {
01328                 vuint32_t:14;
01329                 vuint32_t MSEL:2;
01330                   vuint32_t:8;
01331                 vuint32_t LSEL:8;
01332             } B;
01333         } LMSR;
01334 
01335         union {
01336             vuint32_t R;
01337             struct {
01338                 vuint32_t:28;
01339                 vuint32_t HBSEL:4;
01340             } B;
01341         } HSR;
01342 
01343         union {
01344             vuint32_t R;
01345             struct {
01346                 vuint32_t:10;
01347                 vuint32_t ADDR:19;
01348                   vuint32_t:3;
01349             } B;
01350         } ADR;
01351 
01352         union {                 /* Platform Flash Configuration Register for Port 0 */
01353             vuint32_t R;
01354             struct {
01355                 vuint32_t LBCFG:4;
01356                 vuint32_t ARB:1;
01357                 vuint32_t PRI:1;
01358                   vuint32_t:2;
01359                 vuint32_t M7PFE:1;
01360                 vuint32_t M6PFE:1;
01361                 vuint32_t M5PFE:1;
01362                 vuint32_t M4PFE:1;
01363                 vuint32_t M3PFE:1;
01364                 vuint32_t M2PFE:1;
01365                 vuint32_t M1PFE:1;
01366                 vuint32_t M0PFE:1;
01367                 vuint32_t APC:3;
01368                 vuint32_t WWSC:2;
01369                 vuint32_t RWSC:3;
01370                   vuint32_t:1;
01371                 vuint32_t DPFEN:1;
01372                   vuint32_t:1;
01373                 vuint32_t IPFEN:1;
01374                   vuint32_t:1;
01375                 vuint32_t PFLIM:2;
01376                 vuint32_t BFEN:1;
01377             } B;
01378         } PFCRP0;
01379 
01380         union {                 /* Platform Flash Configuration Register for Port 1 */
01381             vuint32_t R;
01382             struct {
01383                 vuint32_t LBCFG:4;
01384                   vuint32_t:4;
01385                 vuint32_t M7PFE:1;
01386                 vuint32_t M6PFE:1;
01387                 vuint32_t M5PFE:1;
01388                 vuint32_t M4PFE:1;
01389                 vuint32_t M3PFE:1;
01390                 vuint32_t M2PFE:1;
01391                 vuint32_t M1PFE:1;
01392                 vuint32_t M0PFE:1;
01393                 vuint32_t APC:3;
01394                 vuint32_t WWSC:2;
01395                 vuint32_t RWSC:3;
01396                   vuint32_t:1;
01397                 vuint32_t DPFEN:1;
01398                   vuint32_t:1;
01399                 vuint32_t IPFEN:1;
01400                   vuint32_t:1;
01401                 vuint32_t PFLIM:2;
01402                 vuint32_t BFEN:1;
01403             } B;
01404         } PFCRP1;
01405 
01406     };
01407 /****************************************************************************/
01408 /*                          MODULE : FlexCAN                                */
01409 /****************************************************************************/
01410     struct FLEXCAN_tag {
01411         union {
01412             vuint32_t R;
01413             struct {
01414                 vuint32_t MDIS:1;
01415                 vuint32_t FRZ:1;
01416                 vuint32_t FEN:1;
01417                 vuint32_t HALT:1;
01418                 vuint32_t NOTRDY:1;
01419                 vuint32_t WAKMSK:1;
01420                 vuint32_t SOFTRST:1;
01421                 vuint32_t FRZACK:1;
01422                 vuint32_t SUPV:1;
01423                 vuint32_t SLFWAK:1;
01424                 vuint32_t WRNEN:1;
01425                 vuint32_t LPMACK:1;
01426                 vuint32_t WAKSRC:1;
01427                 vuint32_t DOZE:1;
01428                 vuint32_t SRXDIS:1;
01429                 vuint32_t BCC:1;
01430                   vuint32_t:2;
01431                 vuint32_t LPRIO_EN:1;
01432                 vuint32_t AEN:1;
01433                   vuint32_t:2;
01434                 vuint32_t IDAM:2;
01435                   vuint32_t:2;
01436                 vuint32_t MAXMB:6;
01437             } B;
01438         } MCR;                  /* Module Configuration Register */
01439 
01440         union {
01441             vuint32_t R;
01442             struct {
01443                 vuint32_t PRESDIV:8;
01444                 vuint32_t RJW:2;
01445                 vuint32_t PSEG1:3;
01446                 vuint32_t PSEG2:3;
01447                 vuint32_t BOFFMSK:1;
01448                 vuint32_t ERRMSK:1;
01449                 vuint32_t CLKSRC:1;
01450                 vuint32_t LPB:1;
01451                 vuint32_t TWRNMSK:1;
01452                 vuint32_t RWRNMSK:1;
01453                   vuint32_t:2;
01454                 vuint32_t SMP:1;
01455                 vuint32_t BOFFREC:1;
01456                 vuint32_t TSYN:1;
01457                 vuint32_t LBUF:1;
01458                 vuint32_t LOM:1;
01459                 vuint32_t PROPSEG:3;
01460             } B;
01461         } CR;                   /* Control Register */
01462 
01463         union {
01464             vuint32_t R;
01465         } TIMER;                /* Free Running Timer */
01466 
01467         uint32_t FLEXCAN_reserved1;
01468 
01469         union {
01470             vuint32_t R;
01471             struct {
01472                 vuint32_t MI:32;
01473             } B;
01474         } RXGMASK;              /* RX Global Mask */
01475 
01476         union {
01477             vuint32_t R;
01478             struct {
01479                 vuint32_t MI:32;
01480             } B;
01481         } RX14MASK;             /* RX 14 Mask */
01482 
01483         union {
01484             vuint32_t R;
01485             struct {
01486                 vuint32_t MI:32;
01487             } B;
01488         } RX15MASK;             /* RX 15 Mask */
01489 
01490         union {
01491             vuint32_t R;
01492             struct {
01493                 vuint32_t:16;
01494                 vuint32_t RXECNT:8;
01495                 vuint32_t TXECNT:8;
01496             } B;
01497         } ECR;                  /* Error Counter Register */
01498 
01499         union {
01500             vuint32_t R;
01501             struct {
01502                 vuint32_t:14;
01503                 vuint32_t TWRNINT:1;
01504                 vuint32_t RWRNINT:1;
01505                 vuint32_t BIT1ERR:1;
01506                 vuint32_t BIT0ERR:1;
01507                 vuint32_t ACKERR:1;
01508                 vuint32_t CRCERR:1;
01509                 vuint32_t FRMERR:1;
01510                 vuint32_t STFERR:1;
01511                 vuint32_t TXWRN:1;
01512                 vuint32_t RXWRN:1;
01513                 vuint32_t IDLE:1;
01514                 vuint32_t TXRX:1;
01515                 vuint32_t FLTCONF:2;
01516                   vuint32_t:1;
01517                 vuint32_t BOFFINT:1;
01518                 vuint32_t ERRINT:1;
01519                 vuint32_t WAKINT:1;
01520             } B;
01521         } ESR;                  /* Error and Status Register */
01522 
01523         union {
01524             vuint32_t R;
01525             struct {
01526                 vuint32_t BUF63M:1;
01527                 vuint32_t BUF62M:1;
01528                 vuint32_t BUF61M:1;
01529                 vuint32_t BUF60M:1;
01530                 vuint32_t BUF59M:1;
01531                 vuint32_t BUF58M:1;
01532                 vuint32_t BUF57M:1;
01533                 vuint32_t BUF56M:1;
01534                 vuint32_t BUF55M:1;
01535                 vuint32_t BUF54M:1;
01536                 vuint32_t BUF53M:1;
01537                 vuint32_t BUF52M:1;
01538                 vuint32_t BUF51M:1;
01539                 vuint32_t BUF50M:1;
01540                 vuint32_t BUF49M:1;
01541                 vuint32_t BUF48M:1;
01542                 vuint32_t BUF47M:1;
01543                 vuint32_t BUF46M:1;
01544                 vuint32_t BUF45M:1;
01545                 vuint32_t BUF44M:1;
01546                 vuint32_t BUF43M:1;
01547                 vuint32_t BUF42M:1;
01548                 vuint32_t BUF41M:1;
01549                 vuint32_t BUF40M:1;
01550                 vuint32_t BUF39M:1;
01551                 vuint32_t BUF38M:1;
01552                 vuint32_t BUF37M:1;
01553                 vuint32_t BUF36M:1;
01554                 vuint32_t BUF35M:1;
01555                 vuint32_t BUF34M:1;
01556                 vuint32_t BUF33M:1;
01557                 vuint32_t BUF32M:1;
01558             } B;
01559         } IMRH;                 /* Interruput Masks Register */
01560 
01561         union {
01562             vuint32_t R;
01563             struct {
01564                 vuint32_t BUF31M:1;
01565                 vuint32_t BUF30M:1;
01566                 vuint32_t BUF29M:1;
01567                 vuint32_t BUF28M:1;
01568                 vuint32_t BUF27M:1;
01569                 vuint32_t BUF26M:1;
01570                 vuint32_t BUF25M:1;
01571                 vuint32_t BUF24M:1;
01572                 vuint32_t BUF23M:1;
01573                 vuint32_t BUF22M:1;
01574                 vuint32_t BUF21M:1;
01575                 vuint32_t BUF20M:1;
01576                 vuint32_t BUF19M:1;
01577                 vuint32_t BUF18M:1;
01578                 vuint32_t BUF17M:1;
01579                 vuint32_t BUF16M:1;
01580                 vuint32_t BUF15M:1;
01581                 vuint32_t BUF14M:1;
01582                 vuint32_t BUF13M:1;
01583                 vuint32_t BUF12M:1;
01584                 vuint32_t BUF11M:1;
01585                 vuint32_t BUF10M:1;
01586                 vuint32_t BUF09M:1;
01587                 vuint32_t BUF08M:1;
01588                 vuint32_t BUF07M:1;
01589                 vuint32_t BUF06M:1;
01590                 vuint32_t BUF05M:1;
01591                 vuint32_t BUF04M:1;
01592                 vuint32_t BUF03M:1;
01593                 vuint32_t BUF02M:1;
01594                 vuint32_t BUF01M:1;
01595                 vuint32_t BUF00M:1;
01596             } B;
01597         } IMRL;                 /* Interruput Masks Register */
01598 
01599         union {
01600             vuint32_t R;
01601             struct {
01602                 vuint32_t BUF63I:1;
01603                 vuint32_t BUF62I:1;
01604                 vuint32_t BUF61I:1;
01605                 vuint32_t BUF60I:1;
01606                 vuint32_t BUF59I:1;
01607                 vuint32_t BUF58I:1;
01608                 vuint32_t BUF57I:1;
01609                 vuint32_t BUF56I:1;
01610                 vuint32_t BUF55I:1;
01611                 vuint32_t BUF54I:1;
01612                 vuint32_t BUF53I:1;
01613                 vuint32_t BUF52I:1;
01614                 vuint32_t BUF51I:1;
01615                 vuint32_t BUF50I:1;
01616                 vuint32_t BUF49I:1;
01617                 vuint32_t BUF48I:1;
01618                 vuint32_t BUF47I:1;
01619                 vuint32_t BUF46I:1;
01620                 vuint32_t BUF45I:1;
01621                 vuint32_t BUF44I:1;
01622                 vuint32_t BUF43I:1;
01623                 vuint32_t BUF42I:1;
01624                 vuint32_t BUF41I:1;
01625                 vuint32_t BUF40I:1;
01626                 vuint32_t BUF39I:1;
01627                 vuint32_t BUF38I:1;
01628                 vuint32_t BUF37I:1;
01629                 vuint32_t BUF36I:1;
01630                 vuint32_t BUF35I:1;
01631                 vuint32_t BUF34I:1;
01632                 vuint32_t BUF33I:1;
01633                 vuint32_t BUF32I:1;
01634             } B;
01635         } IFRH;                 /* Interruput Flag Register */
01636 
01637         union {
01638             vuint32_t R;
01639             struct {
01640                 vuint32_t BUF31I:1;
01641                 vuint32_t BUF30I:1;
01642                 vuint32_t BUF29I:1;
01643                 vuint32_t BUF28I:1;
01644                 vuint32_t BUF27I:1;
01645                 vuint32_t BUF26I:1;
01646                 vuint32_t BUF25I:1;
01647                 vuint32_t BUF24I:1;
01648                 vuint32_t BUF23I:1;
01649                 vuint32_t BUF22I:1;
01650                 vuint32_t BUF21I:1;
01651                 vuint32_t BUF20I:1;
01652                 vuint32_t BUF19I:1;
01653                 vuint32_t BUF18I:1;
01654                 vuint32_t BUF17I:1;
01655                 vuint32_t BUF16I:1;
01656                 vuint32_t BUF15I:1;
01657                 vuint32_t BUF14I:1;
01658                 vuint32_t BUF13I:1;
01659                 vuint32_t BUF12I:1;
01660                 vuint32_t BUF11I:1;
01661                 vuint32_t BUF10I:1;
01662                 vuint32_t BUF09I:1;
01663                 vuint32_t BUF08I:1;
01664                 vuint32_t BUF07I:1;
01665                 vuint32_t BUF06I:1;
01666                 vuint32_t BUF05I:1;
01667                 vuint32_t BUF04I:1;
01668                 vuint32_t BUF03I:1;
01669                 vuint32_t BUF02I:1;
01670                 vuint32_t BUF01I:1;
01671                 vuint32_t BUF00I:1;
01672             } B;
01673         } IFRL;                 /* Interruput Flag Register */
01674 
01675         uint32_t FLEXCAN_reserved2[19];
01676 
01677         struct canbuf_t {
01678             union {
01679                 vuint32_t R;
01680                 struct {
01681                     vuint32_t:4;
01682                     vuint32_t CODE:4;
01683                       vuint32_t:1;
01684                     vuint32_t SRR:1;
01685                     vuint32_t IDE:1;
01686                     vuint32_t RTR:1;
01687                     vuint32_t LENGTH:4;
01688                     vuint32_t TIMESTAMP:16;
01689                 } B;
01690             } CS;
01691 
01692             union {
01693                 vuint32_t R;
01694                 struct {
01695                     vuint32_t PRIO:3;
01696                     vuint32_t STD_ID:11;
01697                     vuint32_t EXT_ID:18;
01698                 } B;
01699             } ID;
01700 
01701             union {
01702                 //vuint8_t  B[8]; /* Data buffer in Bytes (8 bits) */
01703                 //vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
01704                 vuint32_t W[2]; /* Data buffer in words (32 bits) */
01705                 //vuint32_t R[2];        /* Data buffer in words (32 bits) */
01706             } DATA;
01707 
01708         } BUF[64];
01709 
01710         uint32_t FLEXCAN_reserved3[256];
01711 
01712         union {
01713             vuint32_t R;
01714             struct {
01715                 vuint32_t MI:32;
01716             } B;
01717         } RXIMR[64];            /* RX Individual Mask Registers */
01718 
01719     };
01720 /****************************************************************************/
01721 /*                     MODULE : FMPLL                                       */
01722 /****************************************************************************/
01723     struct FMPLL_tag {
01724 
01725         uint32_t FMPLL_reserved0;
01726 
01727         union {                 /* Synthesiser Status Register */
01728             vuint32_t R;
01729             struct {
01730                 vuint32_t:22;
01731                 vuint32_t LOLF:1;
01732                 vuint32_t LOC:1;
01733                 vuint32_t MODE:1;
01734                 vuint32_t PLLSEL:1;
01735                 vuint32_t PLLREF:1;
01736                 vuint32_t LOCKS:1;
01737                 vuint32_t LOCK:1;
01738                 vuint32_t LOCF:1;
01739                 vuint32_t CALDONE:1;
01740                 vuint32_t CALPASS:1;
01741             } B;
01742         } SYNSR;
01743 
01744         union {
01745             vuint32_t R;
01746             struct {
01747                 vuint32_t EMODE:1;
01748                 vuint32_t CLKCFG:3;
01749                   vuint32_t:8;
01750                 vuint32_t EPREDIV:4;
01751                   vuint32_t:8;
01752                 vuint32_t EMFD:8;
01753             } B;
01754         } ESYNCR1;
01755 
01756         union {
01757             vuint32_t R;
01758             struct {
01759                 vuint32_t:8;
01760                 vuint32_t LOCEN:1;
01761                 vuint32_t LOLRE:1;
01762                 vuint32_t LOCRE:1;
01763                 vuint32_t LOLIRQ:1;
01764                 vuint32_t LOCIRQ:1;
01765                   vuint32_t:1;
01766                 vuint32_t ERATE:2;
01767                   vuint32_t:5;
01768                 vuint32_t EDEPTH:3;
01769                   vuint32_t:2;
01770                 vuint32_t ERFD:6;
01771             } B;
01772         } ESYNCR2;
01773 
01774     };
01775 /****************************************************************************/
01776 /*                          MODULE : i2c                                    */
01777 /****************************************************************************/
01778     struct I2C_tag {
01779         union {
01780             vuint8_t R;
01781             struct {
01782                 vuint8_t ADR:7;
01783                   vuint8_t:1;
01784             } B;
01785         } IBAD;                 /* Module Bus Address Register */
01786 
01787         union {
01788             vuint8_t R;
01789             struct {
01790                 vuint8_t IBC:8;
01791             } B;
01792         } IBFD;                 /* Module Bus Frequency Register */
01793 
01794         union {
01795             vuint8_t R;
01796             struct {
01797                 vuint8_t MDIS:1;
01798                 vuint8_t IBIE:1;
01799                 vuint8_t MS:1;
01800                 vuint8_t TX:1;
01801                 vuint8_t NOACK:1;
01802                 vuint8_t RSTA:1;
01803                 vuint8_t DMAEN:1;
01804                 vuint8_t IBDOZE:1;
01805             } B;
01806         } IBCR;                 /* Module Bus Control Register */
01807 
01808         union {
01809             vuint8_t R;
01810             struct {
01811                 vuint8_t TCF:1;
01812                 vuint8_t IAAS:1;
01813                 vuint8_t IBB:1;
01814                 vuint8_t IBAL:1;
01815                   vuint8_t:1;
01816                 vuint8_t SRW:1;
01817                 vuint8_t IBIF:1;
01818                 vuint8_t RXAK:1;
01819             } B;
01820         } IBSR;                 /* Module Status Register */
01821 
01822         union {
01823             vuint8_t R;
01824             struct {
01825                 vuint8_t DATA:8;
01826             } B;
01827         } IBDR;                 /* Module Data Register */
01828 
01829         union {
01830             vuint8_t R;
01831             struct {
01832                 vuint8_t BIIE:1;
01833                   vuint8_t:7;
01834             } B;
01835         } IBIC;                 /* Module Interrupt Configuration Register */
01836 
01837     };
01838 /****************************************************************************/
01839 /*                          MODULE : INTC                                   */
01840 /****************************************************************************/
01841     struct INTC_tag {
01842         union {
01843             vuint32_t R;
01844             struct {
01845                 vuint32_t:18;
01846                 vuint32_t VTES_PRC1:1;
01847                   vuint32_t:4;
01848                 vuint32_t HVEN_PRC1:1;
01849                   vuint32_t:2;
01850                 vuint32_t VTES_PRC0:1;
01851                   vuint32_t:4;
01852                 vuint32_t HVEN_PRC0:1;
01853             } B;
01854         } MCR;                  /* Module Configuration Register */
01855 
01856         int32_t INTC_reserved1;
01857 
01858         union {
01859             vuint32_t R;
01860             struct {
01861                 vuint32_t:28;
01862                 vuint32_t PRI:4;
01863             } B;
01864         } CPR_PRC0;             /* Processor 0 Current Priority Register */
01865 
01866         union {
01867             vuint32_t R;
01868             struct {
01869                 vuint32_t:28;
01870                 vuint32_t PRI:4;
01871             } B;
01872         } CPR_PRC1;             /* Processor 1 Current Priority Register */
01873 
01874         union {
01875             vuint32_t R;
01876             struct {
01877                 vuint32_t VTBA_PRC0:21;
01878                 vuint32_t INTVEC_PRC0:9;
01879                   vuint32_t:2;
01880             } B;
01881         } IACKR_PRC0;           /* Processor 0 Interrupt Acknowledge Register */
01882 
01883         union {
01884             vuint32_t R;
01885             struct {
01886                 vuint32_t VTBA_PRC1:21;
01887                 vuint32_t INTVEC_PRC1:9;
01888                   vuint32_t:2;
01889             } B;
01890         } IACKR_PRC1;           /* Processor 1 Interrupt Acknowledge Register */
01891 
01892         union {
01893             vuint32_t R;
01894             struct {
01895                 vuint32_t:32;
01896             } B;
01897         } EOIR_PRC0;            /* Processor 0 End of Interrupt Register */
01898 
01899         union {
01900             vuint32_t R;
01901             struct {
01902                 vuint32_t:32;
01903             } B;
01904         } EOIR_PRC1;            /* Processor 1 End of Interrupt Register */
01905 
01906         union {
01907             vuint8_t R;
01908             struct {
01909                 vuint8_t:6;
01910                 vuint8_t SET:1;
01911                 vuint8_t CLR:1;
01912             } B;
01913         } SSCIR[8];             /* Software Set/Clear Interruput Register */
01914 
01915         uint32_t intc_reserved2[6];
01916 
01917         union {
01918             vuint8_t R;
01919             struct {
01920                 vuint8_t PRC_SEL:2;
01921                   vuint8_t:2;
01922                 vuint8_t PRI:4;
01923             } B;
01924         } PSR[294];             /* Software Set/Clear Interrupt Register */
01925 
01926     };
01927 /****************************************************************************/
01928 /*                     MODULE : MCM                                         */
01929 /****************************************************************************/
01930     struct MCM_tag {
01931 
01932         uint32_t mcm_reserved1[5];
01933 
01934         uint16_t mcm_reserved2;
01935 
01936         union {
01937             vuint16_t R;
01938             struct {
01939                 vuint16_t RO:1;
01940                   vuint16_t:6;
01941                 vuint16_t SWRWH:1;
01942                 vuint16_t SWE:1;
01943                 vuint16_t SWRI:2;
01944                 vuint16_t SWT:5;
01945             } B;
01946         } SWTCR;                //Software Watchdog Timer Control
01947 
01948         uint8_t mcm_reserved3[3];
01949 
01950         union {
01951             vuint8_t R;
01952         } SWTSR;                //SWT Service Register
01953 
01954         uint8_t mcm_reserved4[3];
01955 
01956         union {
01957             vuint8_t R;
01958             struct {
01959                 vuint8_t:7;
01960                 vuint8_t SWTIC:1;
01961             } B;
01962         } SWTIR;                //SWT Interrupt Register
01963 
01964         uint32_t mcm_reserved5[1];
01965 
01966         union {
01967             vuint32_t R;
01968             struct {
01969                 vuint32_t PRI:1;
01970                   vuint32_t:31;
01971             } B;
01972         } MUDCR;                //Misc. User Defined Control Register
01973 
01974         uint32_t mcm_reserved6[6];
01975         uint8_t mcm_reserved7[3];
01976 
01977         union {
01978             vuint8_t R;
01979             struct {
01980                 vuint8_t:6;
01981                 vuint8_t ERNCR:1;
01982                 vuint8_t EFNCR:1;
01983             } B;
01984         } ECR;                  //ECC Configuration Register
01985 
01986         uint8_t mcm_reserved8[3];
01987 
01988         union {
01989             vuint8_t R;
01990             struct {
01991                 vuint8_t:6;
01992                 vuint8_t RNCE:1;
01993                 vuint8_t FNCE:1;
01994             } B;
01995         } ESR;                  //ECC Status Register
01996 
01997         uint16_t mcm_reserved9;
01998 
01999         union {
02000             vuint16_t R;
02001             struct {
02002                 vuint16_t:6;
02003                 vuint16_t FRCNCI:1;
02004                 vuint16_t FR1NCI:1;
02005                   vuint16_t:1;
02006                 vuint16_t ERRBIT:7;
02007             } B;
02008         } EEGR;                 //ECC Error Generation Register
02009 
02010         uint32_t mcm_reserved10;
02011 
02012         union {
02013             vuint32_t R;
02014         } FEAR;                 //Flash ECC Address Register
02015 
02016         uint16_t mcm_reserved11;
02017 
02018         union {
02019             vuint8_t R;
02020             struct {
02021                 vuint8_t:4;
02022                 vuint8_t FEMR:4;
02023             } B;
02024         } FEMR;                 //Flash ECC Master Register
02025 
02026         union {
02027             vuint8_t R;
02028             struct {
02029                 vuint8_t WRITE:1;
02030                 vuint8_t SIZE:3;
02031                 vuint8_t PROTECTION:4;
02032             } B;
02033         } FEAT;                 //Flash ECC Attributes Register
02034 
02035         union {
02036             vuint32_t R;
02037         } FEDRH;                //Flash ECC Data High Register
02038 
02039         union {
02040             vuint32_t R;
02041         } FEDRL;                //Flash ECC Data Low Register
02042 
02043         union {
02044             vuint32_t R;
02045             struct {
02046                 vuint32_t REAR:32;
02047             } B;
02048         } REAR;                 //RAM ECC Address
02049 
02050         uint16_t mcm_reserved12;
02051 
02052         union {
02053             vuint8_t R;
02054             struct {
02055                 vuint8_t:4;
02056                 vuint8_t REMR:4;
02057             } B;
02058         } REMR;                 //RAM ECC Master
02059 
02060         union {
02061             vuint8_t R;
02062             struct {
02063                 vuint8_t WRITE:1;
02064                 vuint8_t SIZE:3;
02065                 vuint8_t PROTECTION:1;
02066             } B;
02067         } REAT;                 // RAM ECC Attributes Register
02068 
02069         union {
02070             vuint32_t R;
02071         } REDRH;                //RAM ECC Data High Register
02072 
02073         union {
02074             vuint32_t R;
02075         } REDRL;                //RAMECC Data Low Register
02076 
02077     };
02078 /****************************************************************************/
02079 /*                          MODULE : MPU                                    */
02080 /****************************************************************************/
02081     struct MPU_tag {
02082         union {
02083             vuint32_t R;
02084             struct {
02085                 vuint32_t MSTR:8;
02086                   vuint32_t:4;
02087                 vuint32_t HRL:4;
02088                 vuint32_t NSP:4;
02089                 vuint32_t NGRD:4;
02090                   vuint32_t:7;
02091                 vuint32_t VLD:1;
02092             } B;
02093         } CESR;                 /* Module Control/Error Status Register */
02094 
02095         uint32_t mpu_reserved1[3];
02096 
02097         union {
02098             vuint32_t R;
02099             struct {
02100                 vuint32_t EADDR:32;
02101             } B;
02102         } EAR0;
02103 
02104         union {
02105             vuint32_t R;
02106             struct {
02107                 vuint32_t EACD:16;
02108                 vuint32_t EPID:8;
02109                 vuint32_t EMN:4;
02110                 vuint32_t EATTR:3;
02111                 vuint32_t ERW:1;
02112             } B;
02113         } EDR0;
02114 
02115         union {
02116             vuint32_t R;
02117             struct {
02118                 vuint32_t EADDR:32;
02119             } B;
02120         } EAR1;
02121 
02122         union {
02123             vuint32_t R;
02124             struct {
02125                 vuint32_t EACD:16;
02126                 vuint32_t EPID:8;
02127                 vuint32_t EMN:4;
02128                 vuint32_t EATTR:3;
02129                 vuint32_t ERW:1;
02130             } B;
02131         } EDR1;
02132 
02133         union {
02134             vuint32_t R;
02135             struct {
02136                 vuint32_t EADDR:32;
02137             } B;
02138         } EAR2;
02139 
02140         union {
02141             vuint32_t R;
02142             struct {
02143                 vuint32_t EACD:16;
02144                 vuint32_t EPID:8;
02145                 vuint32_t EMN:4;
02146                 vuint32_t EATTR:3;
02147                 vuint32_t ERW:1;
02148             } B;
02149         } EDR2;
02150 
02151         uint32_t mpu_reserved2[246];
02152 
02153         struct {
02154             union {
02155                 vuint32_t R;
02156                 struct {
02157                     vuint32_t SRTADDR:27;
02158                       vuint32_t:5;
02159                 } B;
02160             } WORD0;            /* Region Descriptor n Word 0 */
02161 
02162             union {
02163                 vuint32_t R;
02164                 struct {
02165                     vuint32_t ENDADDR:27;
02166                       vuint32_t:5;
02167                 } B;
02168             } WORD1;            /* Region Descriptor n Word 1 */
02169 
02170             union {
02171                 vuint32_t R;
02172                 struct {
02173                     vuint32_t:6;
02174                     vuint32_t M4RE0:1;
02175                     vuint32_t M4WE:1;
02176                     vuint32_t M3PE:1;
02177                     vuint32_t M3SM:2;
02178                     vuint32_t M3UM:3;
02179                     vuint32_t M2PE:1;
02180                     vuint32_t M2SM:2;
02181                     vuint32_t M2UM:3;
02182                     vuint32_t M1PE:1;
02183                     vuint32_t M1SM:2;
02184                     vuint32_t M1UM:3;
02185                     vuint32_t M0PE:1;
02186                     vuint32_t M0SM:2;
02187                     vuint32_t M0UM:3;
02188                 } B;
02189             } WORD2;            /* Region Descriptor n Word 2 */
02190 
02191             union {
02192                 vuint32_t R;
02193                 struct {
02194                     vuint32_t PID:8;
02195                     vuint32_t PIDMASK:8;
02196                       vuint32_t:15;
02197                     vuint32_t VLD:1;
02198                 } B;
02199             } WORD3;            /* Region Descriptor n Word 3 */
02200 
02201         } RGD[16];
02202 
02203         uint32_t mpu_reserved3[192];
02204 
02205         union {
02206             vuint32_t R;
02207             struct {
02208                 vuint32_t:6;
02209                 vuint32_t M4RE:1;
02210                 vuint32_t M4WE:1;
02211                 vuint32_t M3PE:1;
02212                 vuint32_t M3SM:2;
02213                 vuint32_t M3UM:3;
02214                 vuint32_t M2PE:1;
02215                 vuint32_t M2SM:2;
02216                 vuint32_t M2UM:3;
02217                 vuint32_t M1PE:1;
02218                 vuint32_t M1SM:2;
02219                 vuint32_t M1UM:3;
02220                 vuint32_t M0PE:1;
02221                 vuint32_t M0SM:2;
02222                 vuint32_t M0UM:3;
02223             } B;
02224         } RGDAAC[16];           /* Region Descriptor Alternate Access Control n */
02225     };
02226 /****************************************************************************/
02227 /*                          MODULE : pit                                    */
02228 /****************************************************************************/
02229     struct PIT_tag {
02230         union {
02231             vuint32_t R;
02232             struct {
02233                 vuint32_t:8;
02234                 vuint32_t TSV:24;
02235             } B;
02236         } TLVAL0;
02237 
02238         union {
02239             vuint32_t R;
02240             struct {
02241                 vuint32_t TSV:32;
02242             } B;
02243         } TLVAL1;
02244 
02245         union {
02246             vuint32_t R;
02247             struct {
02248                 vuint32_t TSV:32;
02249             } B;
02250         } TLVAL2;
02251 
02252         union {
02253             vuint32_t R;
02254             struct {
02255                 vuint32_t TSV:32;
02256             } B;
02257         } TLVAL3;
02258 
02259         union {
02260             vuint32_t R;
02261             struct {
02262                 vuint32_t TSV:32;
02263             } B;
02264         } TLVAL4;
02265 
02266         union {
02267             vuint32_t R;
02268             struct {
02269                 vuint32_t TSV:32;
02270             } B;
02271         } TLVAL5;
02272 
02273         union {
02274             vuint32_t R;
02275             struct {
02276                 vuint32_t TSV:32;
02277             } B;
02278         } TLVAL6;
02279 
02280         union {
02281             vuint32_t R;
02282             struct {
02283                 vuint32_t TSV:32;
02284             } B;
02285         } TLVAL7;
02286 
02287         union {
02288             vuint32_t R;
02289             struct {
02290                 vuint32_t TSV:32;
02291             } B;
02292         } TLVAL8;
02293 
02294         uint32_t pit_reserved1[23];
02295 
02296         union {
02297             vuint32_t R;
02298             struct {
02299                 vuint32_t:8;
02300                 vuint32_t TVL:24;
02301             } B;
02302         } TVAL0;
02303 
02304         union {
02305             vuint32_t R;
02306             struct {
02307                 vuint32_t TVL:32;
02308             } B;
02309         } TVAL1;
02310 
02311         union {
02312             vuint32_t R;
02313             struct {
02314                 vuint32_t TVL:32;
02315             } B;
02316         } TVAL2;
02317 
02318         union {
02319             vuint32_t R;
02320             struct {
02321                 vuint32_t TVL:32;
02322             } B;
02323         } TVAL3;
02324 
02325         union {
02326             vuint32_t R;
02327             struct {
02328                 vuint32_t TVL:32;
02329             } B;
02330         } TVAL4;
02331 
02332         union {
02333             vuint32_t R;
02334             struct {
02335                 vuint32_t TVL:32;
02336             } B;
02337         } TVAL5;
02338 
02339         union {
02340             vuint32_t R;
02341             struct {
02342                 vuint32_t TVL:32;
02343             } B;
02344         } TVAL6;
02345 
02346         union {
02347             vuint32_t R;
02348             struct {
02349                 vuint32_t TVL:32;
02350             } B;
02351         } TVAL7;
02352 
02353         union {
02354             vuint32_t R;
02355             struct {
02356                 vuint32_t TVL:32;
02357             } B;
02358         } TVAL8;
02359 
02360         uint32_t pit_reserved2[23];
02361 
02362         union {
02363             vuint32_t R;
02364             struct {
02365                 vuint32_t:27;
02366                 vuint32_t TIF4:1;
02367                 vuint32_t TIF3:1;
02368                 vuint32_t TIF2:1;
02369                 vuint32_t TIF1:1;
02370                 vuint32_t RTIF:1;
02371             } B;
02372         } FLG;
02373 
02374         union {
02375             vuint32_t R;
02376             struct {
02377                 vuint32_t:27;
02378                 vuint32_t TIE4:1;
02379                 vuint32_t TIE3:1;
02380                 vuint32_t TIE2:1;
02381                 vuint32_t TIE1:1;
02382                 vuint32_t RTIE:1;
02383             } B;
02384         } INTEN;
02385 
02386         union {
02387             vuint32_t R;
02388             struct {
02389                 vuint32_t:27;
02390                 vuint32_t ISEL4:1;
02391                 vuint32_t ISEL3:1;
02392                 vuint32_t ISEL2:1;
02393                 vuint32_t ISEL1:1;
02394                   vuint32_t:1;
02395             } B;
02396         } INTSEL;
02397 
02398         union {
02399             vuint32_t R;
02400             struct {
02401                 vuint32_t:21;
02402                 vuint32_t PEN10:1;
02403                 vuint32_t PEN9:1;
02404                 vuint32_t PEN8:1;
02405                 vuint32_t PEN7:1;
02406                 vuint32_t PEN6:1;
02407                 vuint32_t PEN5:1;
02408                 vuint32_t PEN4:1;
02409                 vuint32_t PEN3:1;
02410                 vuint32_t PEN2:1;
02411                 vuint32_t PEN1:1;
02412                 vuint32_t PEN0:1;
02413             } B;
02414         } EN;
02415 
02416         union {
02417             vuint32_t R;
02418             struct {
02419                 vuint32_t:6;
02420                 vuint32_t DOZE:1;
02421                 vuint32_t MDIS:1;
02422                   vuint32_t:24;
02423             } B;
02424         } CTRL;
02425 
02426     };
02427 /****************************************************************************/
02428 /*                          MODULE : sem4                                   */
02429 /****************************************************************************/
02430     struct SEMA4_tag {
02431         union {
02432             vuint8_t R;
02433             struct {
02434                 vuint8_t:6;
02435                 vuint8_t GTFSM:2;
02436             } B;
02437         } GATE[16];             /* Gate n Register */
02438 
02439         uint32_t sema4_reserved1[12];
02440 
02441         union {
02442             vuint32_t R;
02443             struct {
02444                 vuint32_t INE0:1;
02445                 vuint32_t INE1:1;
02446                 vuint32_t INE2:1;
02447                 vuint32_t INE3:1;
02448                 vuint32_t INE4:1;
02449                 vuint32_t INE5:1;
02450                 vuint32_t INE6:1;
02451                 vuint32_t INE7:1;
02452                 vuint32_t INE8:1;
02453                 vuint32_t INE9:1;
02454                 vuint32_t INE10:1;
02455                 vuint32_t INE11:1;
02456                 vuint32_t INE12:1;
02457                 vuint32_t INE13:1;
02458                 vuint32_t INE14:1;
02459                 vuint32_t INE15:1;
02460                   vuint32_t:16;
02461             } B;
02462         } CP0INE;
02463 
02464         uint32_t sema4_reserved2[1];
02465 
02466         union {
02467             vuint32_t R;
02468             struct {
02469                 vuint32_t INE0:1;
02470                 vuint32_t INE1:1;
02471                 vuint32_t INE2:1;
02472                 vuint32_t INE3:1;
02473                 vuint32_t INE4:1;
02474                 vuint32_t INE5:1;
02475                 vuint32_t INE6:1;
02476                 vuint32_t INE7:1;
02477                 vuint32_t INE8:1;
02478                 vuint32_t INE9:1;
02479                 vuint32_t INE10:1;
02480                 vuint32_t INE11:1;
02481                 vuint32_t INE12:1;
02482                 vuint32_t INE13:1;
02483                 vuint32_t INE14:1;
02484                 vuint32_t INE15:1;
02485                   vuint32_t:16;
02486             } B;
02487         } CP1INE;
02488 
02489         uint32_t sema4_reserved3[13];
02490 
02491         union {
02492             vuint32_t R;
02493             struct {
02494                 vuint32_t GN0:1;
02495                 vuint32_t GN1:1;
02496                 vuint32_t GN2:1;
02497                 vuint32_t GN3:1;
02498                 vuint32_t GN4:1;
02499                 vuint32_t GN5:1;
02500                 vuint32_t GN6:1;
02501                 vuint32_t GN7:1;
02502                 vuint32_t GN8:1;
02503                 vuint32_t GN9:1;
02504                 vuint32_t GN10:1;
02505                 vuint32_t GN11:1;
02506                 vuint32_t GN12:1;
02507                 vuint32_t GN13:1;
02508                 vuint32_t GN14:1;
02509                 vuint32_t GN15:1;
02510                   vuint32_t:16;
02511             } B;
02512         } CP0NTF;
02513 
02514         uint32_t sema4_reserved4[1];
02515 
02516         union {
02517             vuint32_t R;
02518             struct {
02519                 vuint32_t GN0:1;
02520                 vuint32_t GN1:1;
02521                 vuint32_t GN2:1;
02522                 vuint32_t GN3:1;
02523                 vuint32_t GN4:1;
02524                 vuint32_t GN5:1;
02525                 vuint32_t GN6:1;
02526                 vuint32_t GN7:1;
02527                 vuint32_t GN8:1;
02528                 vuint32_t GN9:1;
02529                 vuint32_t GN10:1;
02530                 vuint32_t GN11:1;
02531                 vuint32_t GN12:1;
02532                 vuint32_t GN13:1;
02533                 vuint32_t GN14:1;
02534                 vuint32_t GN15:1;
02535                   vuint32_t:16;
02536             } B;
02537         } CP1NTF;
02538 
02539         uint32_t sema4_reserved5[29];
02540 
02541         union {
02542             vuint32_t R;
02543             struct {
02544                 vuint32_t:2;
02545                 vuint32_t RSTGSM:2;
02546                   vuint32_t:1;
02547                 vuint32_t RSTGMS:3;
02548                 vuint32_t RSTGTN:8;
02549                   vuint32_t:16;
02550             } B;
02551         } RSTGT;
02552 
02553         union {
02554             vuint32_t R;
02555             struct {
02556                 vuint32_t:2;
02557                 vuint32_t RSTNSM:2;
02558                   vuint32_t:1;
02559                 vuint32_t RSTNMS:3;
02560                 vuint32_t RSTNTN:8;
02561                   vuint32_t:16;
02562             } B;
02563         } RSTNTF;
02564     };
02565 /****************************************************************************/
02566 /*                     MODULE : SIU                                         */
02567 /****************************************************************************/
02568     struct SIU_tag {
02569 
02570         int32_t SIU_reserved0;
02571 
02572         union {                 /* MCU ID Register */
02573             vuint32_t R;
02574             struct {
02575                 vuint32_t PARTNUM:16;
02576                 vuint32_t PKG:4;
02577                 vuint32_t MASKNUM:12;
02578             } B;
02579         } MIDR;
02580 
02581         int32_t SIU_reserved1;
02582 
02583         union {                 /* Reset Status Register */
02584             vuint32_t R;
02585             struct {
02586                 vuint32_t PORS:1;
02587                 vuint32_t ERS:1;
02588                 vuint32_t LLRS:1;
02589                 vuint32_t LCRS:1;
02590                 vuint32_t WDRS:1;
02591                 vuint32_t CRS0:1;
02592                 vuint32_t CRS1:1;
02593                   vuint32_t:7;
02594                 vuint32_t SSRS:1;
02595                   vuint32_t:14;
02596                 vuint32_t BOOTCFG:2;
02597                   vuint32_t:1;
02598             } B;
02599         } RSR;
02600 
02601         union {                 /* System Reset Control Register */
02602             vuint32_t R;
02603             struct {
02604                 vuint32_t SSR:1;
02605                   vuint32_t:15;
02606                 vuint32_t CRE0:1;
02607                 vuint32_t CRE1:1;
02608                   vuint32_t:6;
02609                 vuint32_t SSRL:1;
02610                   vuint32_t:7;
02611             } B;
02612         } SRCR;
02613 
02614         union {                 /* External Interrupt Status Register */
02615             vuint32_t R;
02616             struct {
02617                 vuint32_t NMI0:1;
02618                 vuint32_t NMI1:1;
02619                   vuint32_t:14;
02620                 vuint32_t EIF15:1;
02621                 vuint32_t EIF14:1;
02622                 vuint32_t EIF13:1;
02623                 vuint32_t EIF12:1;
02624                 vuint32_t EIF11:1;
02625                 vuint32_t EIF10:1;
02626                 vuint32_t EIF9:1;
02627                 vuint32_t EIF8:1;
02628                 vuint32_t EIF7:1;
02629                 vuint32_t EIF6:1;
02630                 vuint32_t EIF5:1;
02631                 vuint32_t EIF4:1;
02632                 vuint32_t EIF3:1;
02633                 vuint32_t EIF2:1;
02634                 vuint32_t EIF1:1;
02635                 vuint32_t EIF0:1;
02636             } B;
02637         } EISR;
02638 
02639         union {                 /* DMA/Interrupt Request Enable Register */
02640             vuint32_t R;
02641             struct {
02642                 vuint32_t NRE0:1;
02643                 vuint32_t NRE1:1;
02644                   vuint32_t:14;
02645                 vuint32_t EIRE15:1;
02646                 vuint32_t EIRE14:1;
02647                 vuint32_t EIRE13:1;
02648                 vuint32_t EIRE12:1;
02649                 vuint32_t EIRE11:1;
02650                 vuint32_t EIRE10:1;
02651                 vuint32_t EIRE9:1;
02652                 vuint32_t EIRE8:1;
02653                 vuint32_t EIRE7:1;
02654                 vuint32_t EIRE6:1;
02655                 vuint32_t EIRE5:1;
02656                 vuint32_t EIRE4:1;
02657                 vuint32_t EIRE3:1;
02658                 vuint32_t EIRE2:1;
02659                 vuint32_t EIRE1:1;
02660                 vuint32_t EIRE0:1;
02661             } B;
02662         } DIRER;
02663 
02664         union {                 /* DMA/Interrupt Select Register */
02665             vuint32_t R;
02666             struct {
02667                 vuint32_t:28;
02668                 vuint32_t DIRS3:1;
02669                 vuint32_t DIRS2:1;
02670                 vuint32_t DIRS1:1;
02671                 vuint32_t DIRS0:1;
02672             } B;
02673         } DIRSR;
02674 
02675         union {                 /* Overrun Status Register */
02676             vuint32_t R;
02677             struct {
02678                 vuint32_t:16;
02679                 vuint32_t OVF15:1;
02680                 vuint32_t OVF14:1;
02681                 vuint32_t OVF13:1;
02682                 vuint32_t OVF12:1;
02683                 vuint32_t OVF11:1;
02684                 vuint32_t OVF10:1;
02685                 vuint32_t OVF9:1;
02686                 vuint32_t OVF8:1;
02687                 vuint32_t OVF7:1;
02688                 vuint32_t OVF6:1;
02689                 vuint32_t OVF5:1;
02690                 vuint32_t OVF4:1;
02691                 vuint32_t OVF3:1;
02692                 vuint32_t OVF2:1;
02693                 vuint32_t OVF1:1;
02694                 vuint32_t OVF0:1;
02695             } B;
02696         } OSR;
02697 
02698         union {                 /* Overrun Request Enable Register */
02699             vuint32_t R;
02700             struct {
02701                 vuint32_t:16;
02702                 vuint32_t ORE15:1;
02703                 vuint32_t ORE14:1;
02704                 vuint32_t ORE13:1;
02705                 vuint32_t ORE12:1;
02706                 vuint32_t ORE11:1;
02707                 vuint32_t ORE10:1;
02708                 vuint32_t ORE9:1;
02709                 vuint32_t ORE8:1;
02710                 vuint32_t ORE7:1;
02711                 vuint32_t ORE6:1;
02712                 vuint32_t ORE5:1;
02713                 vuint32_t ORE4:1;
02714                 vuint32_t ORE3:1;
02715                 vuint32_t ORE2:1;
02716                 vuint32_t ORE1:1;
02717                 vuint32_t ORE0:1;
02718             } B;
02719         } ORER;
02720 
02721         union {                 /* External IRQ Rising-Edge Event Enable Register */
02722             vuint32_t R;
02723             struct {
02724                 vuint32_t NREE0:1;
02725                 vuint32_t NREE1:1;
02726                   vuint32_t:14;
02727                 vuint32_t IREE15:1;
02728                 vuint32_t IREE14:1;
02729                 vuint32_t IREE13:1;
02730                 vuint32_t IREE12:1;
02731                 vuint32_t IREE11:1;
02732                 vuint32_t IREE10:1;
02733                 vuint32_t IREE9:1;
02734                 vuint32_t IREE8:1;
02735                 vuint32_t IREE7:1;
02736                 vuint32_t IREE6:1;
02737                 vuint32_t IREE5:1;
02738                 vuint32_t IREE4:1;
02739                 vuint32_t IREE3:1;
02740                 vuint32_t IREE2:1;
02741                 vuint32_t IREE1:1;
02742                 vuint32_t IREE0:1;
02743             } B;
02744         } IREER;
02745 
02746         union {                 /* External IRQ Falling-Edge Event Enable Register */
02747             vuint32_t R;
02748             struct {
02749                 vuint32_t NFEE0:1;
02750                 vuint32_t NFEE1:1;
02751                   vuint32_t:14;
02752                 vuint32_t IFEE15:1;
02753                 vuint32_t IFEE14:1;
02754                 vuint32_t IFEE13:1;
02755                 vuint32_t IFEE12:1;
02756                 vuint32_t IFEE11:1;
02757                 vuint32_t IFEE10:1;
02758                 vuint32_t IFEE9:1;
02759                 vuint32_t IFEE8:1;
02760                 vuint32_t IFEE7:1;
02761                 vuint32_t IFEE6:1;
02762                 vuint32_t IFEE5:1;
02763                 vuint32_t IFEE4:1;
02764                 vuint32_t IFEE3:1;
02765                 vuint32_t IFEE2:1;
02766                 vuint32_t IFEE1:1;
02767                 vuint32_t IFEE0:1;
02768             } B;
02769         } IFEER;
02770 
02771         union {                 /* External IRQ Digital Filter Register */
02772             vuint32_t R;
02773             struct {
02774                 vuint32_t:28;
02775                 vuint32_t DFL:4;
02776             } B;
02777         } IDFR;
02778 
02779         union {                 /* External IRQ Filtered Input Register */
02780             vuint32_t R;
02781             struct {
02782                 vuint32_t:16;
02783                 vuint32_t FI15:1;
02784                 vuint32_t FI14:1;
02785                 vuint32_t FI13:1;
02786                 vuint32_t FI12:1;
02787                 vuint32_t FI11:1;
02788                 vuint32_t FI10:1;
02789                 vuint32_t FI9:1;
02790                 vuint32_t FI8:1;
02791                 vuint32_t FI7:1;
02792                 vuint32_t FI6:1;
02793                 vuint32_t FI5:1;
02794                 vuint32_t FI4:1;
02795                 vuint32_t FI3:1;
02796                 vuint32_t FI2:1;
02797                 vuint32_t FI1:1;
02798                 vuint32_t FI0:1;
02799             } B;
02800         } IFIR;
02801 
02802         int32_t SIU_reserved2[2];
02803 
02804         union {                 /* Pad Configuration Registers */
02805             vuint16_t R;
02806             struct {
02807                 vuint16_t:4;
02808                 vuint16_t PA:2;
02809                 vuint16_t OBE:1;
02810                 vuint16_t IBE:1;
02811                   vuint16_t:2;
02812                 vuint16_t ODE:1;
02813                 vuint16_t HYS:1;
02814                 vuint16_t SEC:2;
02815                 vuint16_t WPE:1;
02816                 vuint16_t WPS:1;
02817             } B;
02818         } PCR[146];
02819 
02820         int32_t SIU_reserved3[295];
02821 
02822         union {                 /* GPIO Pin Data Output Registers */
02823             vuint8_t R;
02824             struct {
02825                 vuint8_t:7;
02826                 vuint8_t PDO:1;
02827             } B;
02828         } GPDO[146];
02829 
02830         int32_t SIU_reserved4[91];
02831 
02832         union {                 /* GPIO Pin Data Input Registers */
02833             vuint8_t R;
02834             struct {
02835                 vuint8_t:7;
02836                 vuint8_t PDI:1;
02837             } B;
02838         } GPDI[146];
02839 
02840         int32_t SIU_reserved5[27];
02841 
02842         union {                 /* IMUX Register */
02843             vuint32_t R;
02844             struct {
02845                 vuint32_t TSEL3:2;
02846                 vuint32_t TSEL2:2;
02847                 vuint32_t TSEL1:2;
02848                 vuint32_t TSEL0:2;
02849                   vuint32_t:24;
02850             } B;
02851         } ISEL0;
02852 
02853         union {                 /* IMUX Register */
02854             vuint32_t R;
02855             struct {
02856                 vuint32_t ESEL15:2;
02857                 vuint32_t ESEL14:2;
02858                 vuint32_t ESEL13:2;
02859                 vuint32_t ESEL12:2;
02860                 vuint32_t ESEL11:2;
02861                 vuint32_t ESEL10:2;
02862                 vuint32_t ESEL9:2;
02863                 vuint32_t ESEL8:2;
02864                 vuint32_t ESEL7:2;
02865                 vuint32_t ESEL6:2;
02866                 vuint32_t ESEL5:2;
02867                 vuint32_t ESEL4:2;
02868                 vuint32_t ESEL3:2;
02869                 vuint32_t ESEL2:2;
02870                 vuint32_t ESEL1:2;
02871                 vuint32_t ESEL0:2;
02872             } B;
02873         } ISEL1;
02874 
02875         union {                 /* IMUX Register */
02876             vuint32_t R;
02877             struct {
02878                 vuint32_t SELEMIOS15:2;
02879                 vuint32_t SELEMIOS14:2;
02880                 vuint32_t SELEMIOS13:2;
02881                 vuint32_t SELEMIOS12:2;
02882                 vuint32_t SELEMIOS11:2;
02883                 vuint32_t SELEMIOS10:2;
02884                 vuint32_t SELEMIOS9:2;
02885                 vuint32_t SELEMIOS8:2;
02886                 vuint32_t SELEMIOS7:2;
02887                 vuint32_t SELEMIOS6:2;
02888                 vuint32_t SELEMIOS5:2;
02889                 vuint32_t SELEMIOS4:2;
02890                 vuint32_t SELEMIOS3:2;
02891                 vuint32_t SELEMIOS2:2;
02892                 vuint32_t SELEMIOS1:2;
02893                 vuint32_t SELEMIOS0:2;
02894             } B;
02895         } ISEL2;
02896 
02897         int32_t SIU_reserved6[29];
02898 
02899         union {                 /* Chip Configuration Register Register */
02900             vuint32_t R;
02901             struct {
02902                 vuint32_t:14;
02903                 vuint32_t MATCH:1;
02904                 vuint32_t DISNEX:1;
02905                   vuint32_t:16;
02906             } B;
02907         } CCR;
02908 
02909         union {                 /* External Clock Configuration Register Register */
02910             vuint32_t R;
02911             struct {
02912                 vuint32_t:30;
02913                 vuint32_t EBDF:2;
02914             } B;
02915         } ECCR;
02916 
02917         union {                 /* Compare A High Register */
02918             vuint32_t R;
02919         } CMPAH;
02920 
02921         union {                 /* Compare A Low Register */
02922             vuint32_t R;
02923         } CMPAL;
02924 
02925         union {                 /* Compare B High Register */
02926             vuint32_t R;
02927         } CMPBH;
02928 
02929         union {                 /* Compare B Low Register */
02930             vuint32_t R;
02931         } CMPBL;
02932 
02933         int32_t SIU_reserved7[2];
02934 
02935         union {                 /* System CLock Register */
02936             vuint32_t R;
02937             struct {
02938                 vuint32_t SYSCLKSEL:2;
02939                 vuint32_t SYSCLKDIV:2;
02940                 vuint32_t SWTCLKSEL:1;
02941                   vuint32_t:11;
02942                 vuint32_t LPCLKDIV7:2;
02943                 vuint32_t LPCLKDIV6:2;
02944                 vuint32_t LPCLKDIV5:2;
02945                 vuint32_t LPCLKDIV4:2;
02946                 vuint32_t LPCLKDIV3:2;
02947                 vuint32_t LPCLKDIV2:2;
02948                 vuint32_t LPCLKDIV1:2;
02949                 vuint32_t LPCLKDIV0:2;
02950             } B;
02951         } SYSCLK;
02952 
02953         union {                 /* Halt Register */
02954             vuint32_t R;
02955         } HLT;
02956 
02957         union {                 /* Halt Acknowledge Register */
02958             vuint32_t R;
02959         } HLTACK;
02960 
02961         int32_t SIU_reserved8[149];
02962 
02963         union {                 /* Parallel GPIO Pin Data Output Register */
02964             vuint32_t R;
02965             struct {
02966                 vuint32_t PA:16;
02967                 vuint32_t PB:16;
02968             } B;
02969         } PGPDO0;
02970 
02971         union {                 /* Parallel GPIO Pin Data Output Register */
02972             vuint32_t R;
02973             struct {
02974                 vuint32_t PC:16;
02975                 vuint32_t PD:16;
02976             } B;
02977         } PGPDO1;
02978 
02979         union {                 /* Parallel GPIO Pin Data Output Register */
02980             vuint32_t R;
02981             struct {
02982                 vuint32_t PE:16;
02983                 vuint32_t PF:16;
02984             } B;
02985         } PGPDO2;
02986 
02987         union {                 /* Parallel GPIO Pin Data Output Register */
02988             vuint32_t R;
02989             struct {
02990                 vuint32_t PG:16;
02991                 vuint32_t PH:16;
02992             } B;
02993         } PGPDO3;
02994 
02995         union {                 /* Parallel GPIO Pin Data Output Register */
02996             vuint32_t R;
02997             struct {
02998                 vuint32_t PJ:16;
02999                 vuint32_t PK:2;
03000                   vuint32_t:14;
03001             } B;
03002         } PGPDO4;
03003 
03004         int32_t SIU_reserved9[11];
03005 
03006         union {                 /* Parallel GPIO Pin Data Input Register */
03007             vuint32_t R;
03008             struct {
03009                 vuint32_t PA:16;
03010                 vuint32_t PB:16;
03011             } B;
03012         } PGPDI0;
03013 
03014         union {                 /* Parallel GPIO Pin Data Input Register */
03015             vuint32_t R;
03016             struct {
03017                 vuint32_t PC:16;
03018                 vuint32_t PD:16;
03019             } B;
03020         } PGPDI1;
03021 
03022         union {                 /* Parallel GPIO Pin Data Input Register */
03023             vuint32_t R;
03024             struct {
03025                 vuint32_t PE:16;
03026                 vuint32_t PF:16;
03027             } B;
03028         } PGPDI2;
03029 
03030         union {                 /* Parallel GPIO Pin Data Input Register */
03031             vuint32_t R;
03032             struct {
03033                 vuint32_t PG:16;
03034                 vuint32_t PH:16;
03035             } B;
03036         } PGPDI3;
03037 
03038         union {                 /* Parallel GPIO Pin Data Input Register */
03039             vuint32_t R;
03040             struct {
03041                 vuint32_t PJ:16;
03042                 vuint32_t PK:2;
03043                   vuint32_t:14;
03044             } B;
03045         } PGPDI4;
03046 
03047         int32_t SIU_reserved10[11];
03048 
03049         union {                 /* Masked Parallel GPIO Pin Data Input Register */
03050             vuint32_t R;
03051             struct {
03052                 vuint32_t PA_MASK:16;
03053                 vuint32_t PA:16;
03054             } B;
03055         } MPGPDO0;
03056 
03057         union {                 /* Masked Parallel GPIO Pin Data Input Register */
03058             vuint32_t R;
03059             struct {
03060                 vuint32_t PB_MASK:16;
03061                 vuint32_t PB:16;
03062             } B;
03063         } MPGPDO1;
03064 
03065         union {                 /* Masked Parallel GPIO Pin Data Input Register */
03066             vuint32_t R;
03067             struct {
03068                 vuint32_t PC_MASK:16;
03069                 vuint32_t PC:16;
03070             } B;
03071         } MPGPDO2;
03072 
03073         union {                 /* Masked Parallel GPIO Pin Data Input Register */
03074             vuint32_t R;
03075             struct {
03076                 vuint32_t PD_MASK:16;
03077                 vuint32_t PD:16;
03078             } B;
03079         } MPGPDO3;
03080 
03081         union {                 /* Masked Parallel GPIO Pin Data Input Register */
03082             vuint32_t R;
03083             struct {
03084                 vuint32_t PE_MASK:16;
03085                 vuint32_t PE:16;
03086             } B;
03087         } MPGPDO4;
03088 
03089         union {                 /* Masked Parallel GPIO Pin Data Input Register */
03090             vuint32_t R;
03091             struct {
03092                 vuint32_t PF_MASK:16;
03093                 vuint32_t PF:16;
03094             } B;
03095         } MPGPDO5;
03096 
03097         union {                 /* Masked Parallel GPIO Pin Data Input Register */
03098             vuint32_t R;
03099             struct {
03100                 vuint32_t PG_MASK:16;
03101                 vuint32_t PG:16;
03102             } B;
03103         } MPGPDO6;
03104 
03105         union {                 /* Masked Parallel GPIO Pin Data Input Register */
03106             vuint32_t R;
03107             struct {
03108                 vuint32_t PH_MASK:16;
03109                 vuint32_t PH:16;
03110             } B;
03111         } MPGPDO7;
03112 
03113         union {                 /* Masked Parallel GPIO Pin Data Input Register */
03114             vuint32_t R;
03115             struct {
03116                 vuint32_t PJ_MASK:16;
03117                 vuint32_t PJ:16;
03118             } B;
03119         } MPGPDO8;
03120 
03121     };
03122 /****************************************************************************/
03123 /*                          MODULE : FlexRay                                */
03124 /****************************************************************************/
03125 
03126     typedef union uMVR {
03127         vuint16_t R;
03128         struct {
03129             vuint16_t CHIVER:8; /* CHI Version Number */
03130             vuint16_t PEVER:8;  /* PE Version Number */
03131         } B;
03132     } MVR_t;
03133 
03134     typedef union uMCR {
03135         vuint16_t R;
03136         struct {
03137             vuint16_t MEN:1;    /* module enable */
03138               vuint16_t:1;
03139             vuint16_t SCMD:1;   /* single channel mode */
03140             vuint16_t CHB:1;    /* channel B enable */
03141             vuint16_t CHA:1;    /* channel A enable */
03142             vuint16_t SFFE:1;   /* synchronization frame filter enable */
03143               vuint16_t:5;
03144             vuint16_t CLKSEL:1; /* protocol engine clock source select */
03145             vuint16_t PRESCALE:3;       /* protocol engine clock prescaler */
03146               vuint16_t:1;
03147         } B;
03148     } MCR_t;
03149     typedef union uSTBSCR {
03150         vuint16_t R;
03151         struct {
03152             vuint16_t WMD:1;    /* write mode */
03153             vuint16_t STBSSEL:7;        /* strobe signal select */
03154               vuint16_t:3;
03155             vuint16_t ENB:1;    /* strobe signal enable */
03156               vuint16_t:2;
03157             vuint16_t STBPSEL:2;        /* strobe port select */
03158         } B;
03159     } STBSCR_t;
03160     typedef union uSTBPCR {
03161         vuint16_t R;
03162         struct {
03163             vuint16_t:12;
03164             vuint16_t STB3EN:1; /* strobe port enable */
03165             vuint16_t STB2EN:1; /* strobe port enable */
03166             vuint16_t STB1EN:1; /* strobe port enable */
03167             vuint16_t STB0EN:1; /* strobe port enable */
03168         } B;
03169     } STBPCR_t;
03170 
03171     typedef union uMBDSR {
03172         vuint16_t R;
03173         struct {
03174             vuint16_t:1;
03175             vuint16_t MBSEG2DS:7;       /* message buffer segment 2 data size */
03176               vuint16_t:1;
03177             vuint16_t MBSEG1DS:7;       /* message buffer segment 1 data size */
03178         } B;
03179     } MBDSR_t;
03180 
03181     typedef union uMBSSUTR {
03182         vuint16_t R;
03183         struct {
03184 
03185             vuint16_t:2;
03186             vuint16_t LAST_MB_SEG1:6;   /* last message buffer control register for message buffer segment 1 */
03187               vuint16_t:2;
03188             vuint16_t LAST_MB_UTIL:6;   /* last message buffer utilized */
03189         } B;
03190     } MBSSUTR_t;
03191 
03192     typedef union uPOCR {
03193         vuint16_t R;
03194         vuint8_t byte[2];
03195         struct {
03196             vuint16_t WME:1;    /* write mode external correction command */
03197               vuint16_t:3;
03198             vuint16_t EOC_AP:2; /* external offset correction application */
03199             vuint16_t ERC_AP:2; /* external rate correction application */
03200             vuint16_t BSY:1;    /* command write busy / write mode command */
03201               vuint16_t:3;
03202             vuint16_t POCCMD:4; /* protocol command */
03203         } B;
03204     } POCR_t;
03205 /* protocol commands */
03206     typedef union uGIFER {
03207         vuint16_t R;
03208         struct {
03209             vuint16_t MIF:1;    /* module interrupt flag */
03210             vuint16_t PRIF:1;   /* protocol interrupt flag */
03211             vuint16_t CHIF:1;   /* CHI interrupt flag */
03212             vuint16_t WKUPIF:1; /* wakeup interrupt flag */
03213             vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
03214             vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
03215             vuint16_t RBIF:1;   /* receive message buffer interrupt flag */
03216             vuint16_t TBIF:1;   /* transmit buffer interrupt flag */
03217             vuint16_t MIE:1;    /* module interrupt enable */
03218             vuint16_t PRIE:1;   /* protocol interrupt enable */
03219             vuint16_t CHIE:1;   /* CHI interrupt enable */
03220             vuint16_t WKUPIE:1; /* wakeup interrupt enable */
03221             vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
03222             vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
03223             vuint16_t RBIE:1;   /* receive message buffer interrupt enable */
03224             vuint16_t TBIE:1;   /* transmit buffer interrupt enable */
03225         } B;
03226     } GIFER_t;
03227     typedef union uPIFR0 {
03228         vuint16_t R;
03229         struct {
03230             vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */
03231             vuint16_t INTLIF:1; /* internal protocol error interrupt flag */
03232             vuint16_t ILCFIF:1; /* illegal protocol configuration flag */
03233             vuint16_t CSAIF:1;  /* cold start abort interrupt flag */
03234             vuint16_t MRCIF:1;  /* missing rate correctio interrupt flag */
03235             vuint16_t MOCIF:1;  /* missing offset correctio interrupt flag */
03236             vuint16_t CCLIF:1;  /* clock correction limit reached interrupt flag */
03237             vuint16_t MXSIF:1;  /* max sync frames detected interrupt flag */
03238             vuint16_t MTXIF:1;  /* media access test symbol received flag */
03239             vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
03240             vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
03241             vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
03242             vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
03243             vuint16_t TI2IF:1;  /* timer 2 expired interrupt flag */
03244             vuint16_t TI1IF:1;  /* timer 1 expired interrupt flag */
03245             vuint16_t CYSIF:1;  /* cycle start interrupt flag */
03246         } B;
03247     } PIFR0_t;
03248     typedef union uPIFR1 {
03249         vuint16_t R;
03250         struct {
03251             vuint16_t EMCIF:1;  /* error mode changed interrupt flag */
03252             vuint16_t IPCIF:1;  /* illegal protocol command interrupt flag */
03253             vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
03254             vuint16_t PSCIF:1;  /* Protocol State Changed Interrupt Flag */
03255             vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
03256             vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
03257             vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
03258             vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
03259               vuint16_t:2;
03260             vuint16_t EVTIF:1;  /* even cycle table written interrupt flag */
03261             vuint16_t ODTIF:1;  /* odd cycle table written interrupt flag */
03262               vuint16_t:4;
03263         } B;
03264     } PIFR1_t;
03265     typedef union uPIER0 {
03266         vuint16_t R;
03267         struct {
03268             vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */
03269             vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable  */
03270             vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
03271             vuint16_t CSAIE:1;  /* cold start abort interrupt enable */
03272             vuint16_t MRCIE:1;  /* missing rate correctio interrupt enable */
03273             vuint16_t MOCIE:1;  /* missing offset correctio interrupt enable */
03274             vuint16_t CCLIE:1;  /* clock correction limit reached interrupt enable */
03275             vuint16_t MXSIE:1;  /* max sync frames detected interrupt enable */
03276             vuint16_t MTXIE:1;  /* media access test symbol received interrupt enable */
03277             vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
03278             vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
03279             vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
03280             vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
03281             vuint16_t TI2IE:1;  /* timer 2 expired interrupt enable */
03282             vuint16_t TI1IE:1;  /* timer 1 expired interrupt enable */
03283             vuint16_t CYSIE:1;  /* cycle start interrupt enable */
03284         } B;
03285     } PIER0_t;
03286     typedef union uPIER1 {
03287         vuint16_t R;
03288         struct {
03289             vuint16_t EMCIE:1;  /* error mode changed interrupt enable */
03290             vuint16_t IPCIE:1;  /* illegal protocol command interrupt enable */
03291             vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
03292             vuint16_t PSCIE:1;  /* Protocol State Changed Interrupt enable */
03293             vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
03294             vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
03295             vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
03296             vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
03297               vuint16_t:2;
03298             vuint16_t EVTIE:1;  /* even cycle table written interrupt enable */
03299             vuint16_t ODTIE:1;  /* odd cycle table written interrupt enable */
03300               vuint16_t:4;
03301         } B;
03302     } PIER1_t;
03303     typedef union uCHIERFR {
03304         vuint16_t R;
03305         struct {
03306             vuint16_t FRLBEF:1; /* flame lost channel B error flag */
03307             vuint16_t FRLAEF:1; /* frame lost channel A error flag */
03308             vuint16_t PCMIEF:1; /* command ignored error flag */
03309             vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
03310             vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
03311             vuint16_t MSBEF:1;  /* message buffer search error flag */
03312             vuint16_t MBUEF:1;  /* message buffer utilization error flag */
03313             vuint16_t LCKEF:1;  /* lock error flag */
03314             vuint16_t DBLEF:1;  /* double transmit message buffer lock error flag */
03315             vuint16_t SBCFEF:1; /* system bus communication failure error flag */
03316             vuint16_t FIDEF:1;  /* frame ID error flag */
03317             vuint16_t DPLEF:1;  /* dynamic payload length error flag */
03318             vuint16_t SPLEF:1;  /* static payload length error flag */
03319             vuint16_t NMLEF:1;  /* network management length error flag */
03320             vuint16_t NMFEF:1;  /* network management frame error flag */
03321             vuint16_t ILSAEF:1; /* illegal access error flag */
03322         } B;
03323     } CHIERFR_t;
03324     typedef union uMBIVEC {
03325         vuint16_t R;
03326         struct {
03327 
03328             vuint16_t:2;
03329             vuint16_t TBIVEC:6; /* transmit buffer interrupt vector */
03330               vuint16_t:2;
03331             vuint16_t RBIVEC:6; /* receive buffer interrupt vector */
03332         } B;
03333     } MBIVEC_t;
03334 
03335     typedef union uPSR0 {
03336         vuint16_t R;
03337         struct {
03338             vuint16_t ERRMODE:2;        /* error mode */
03339             vuint16_t SLOTMODE:2;       /* slot mode */
03340               vuint16_t:1;
03341             vuint16_t PROTSTATE:3;      /* protocol state */
03342             vuint16_t SUBSTATE:4;       /* protocol sub state */
03343               vuint16_t:1;
03344             vuint16_t WAKEUPSTATUS:3;   /* wakeup status */
03345         } B;
03346     } PSR0_t;
03347 
03348 /* protocol states */
03349 /* protocol sub-states */
03350 /* wakeup status */
03351     typedef union uPSR1 {
03352         vuint16_t R;
03353         struct {
03354             vuint16_t CSAA:1;   /* cold start attempt abort flag */
03355             vuint16_t SCP:1;    /* cold start path */
03356               vuint16_t:1;
03357             vuint16_t REMCSAT:5;        /* remanining coldstart attempts */
03358             vuint16_t CPN:1;    /* cold start noise path */
03359             vuint16_t HHR:1;    /* host halt request pending */
03360             vuint16_t FRZ:1;    /* freeze occured */
03361             vuint16_t APTAC:5;  /* allow passive to active counter */
03362         } B;
03363     } PSR1_t;
03364     typedef union uPSR2 {
03365         vuint16_t R;
03366         struct {
03367             vuint16_t NBVB:1;   /* NIT boundary violation on channel B */
03368             vuint16_t NSEB:1;   /* NIT syntax error on channel B */
03369             vuint16_t STCB:1;   /* symbol window transmit conflict on channel B */
03370             vuint16_t SBVB:1;   /* symbol window boundary violation on channel B */
03371             vuint16_t SSEB:1;   /* symbol window syntax error on channel B */
03372             vuint16_t MTB:1;    /* media access test symbol MTS received on channel B */
03373             vuint16_t NBVA:1;   /* NIT boundary violation on channel A */
03374             vuint16_t NSEA:1;   /* NIT syntax error on channel A */
03375             vuint16_t STCA:1;   /* symbol window transmit conflict on channel A */
03376             vuint16_t SBVA:1;   /* symbol window boundary violation on channel A */
03377             vuint16_t SSEA:1;   /* symbol window syntax error on channel A */
03378             vuint16_t MTA:1;    /* media access test symbol MTS received on channel A */
03379             vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
03380         } B;
03381     } PSR2_t;
03382     typedef union uPSR3 {
03383         vuint16_t R;
03384         struct {
03385             vuint16_t:2;
03386             vuint16_t WUB:1;    /* wakeup symbol received on channel B */
03387             vuint16_t ABVB:1;   /* aggregated boundary violation on channel B */
03388             vuint16_t AACB:1;   /* aggregated additional communication on channel B */
03389             vuint16_t ACEB:1;   /* aggregated content error on channel B */
03390             vuint16_t ASEB:1;   /* aggregated syntax error on channel B */
03391             vuint16_t AVFB:1;   /* aggregated valid frame on channel B */
03392               vuint16_t:2;
03393             vuint16_t WUA:1;    /* wakeup symbol received on channel A */
03394             vuint16_t ABVA:1;   /* aggregated boundary violation on channel A */
03395             vuint16_t AACA:1;   /* aggregated additional communication on channel A */
03396             vuint16_t ACEA:1;   /* aggregated content error on channel A */
03397             vuint16_t ASEA:1;   /* aggregated syntax error on channel A */
03398             vuint16_t AVFA:1;   /* aggregated valid frame on channel A */
03399         } B;
03400     } PSR3_t;
03401     typedef union uCIFRR {
03402         vuint16_t R;
03403         struct {
03404             vuint16_t:8;
03405             vuint16_t MIFR:1;   /* module interrupt flag */
03406             vuint16_t PRIFR:1;  /* protocol interrupt flag */
03407             vuint16_t CHIFR:1;  /* CHI interrupt flag */
03408             vuint16_t WUPIFR:1; /* wakeup interrupt flag */
03409             vuint16_t FNEBIFR:1;        /* receive fifo channel B no empty interrupt flag */
03410             vuint16_t FNEAIFR:1;        /* receive fifo channel A no empty interrupt flag */
03411             vuint16_t RBIFR:1;  /* receive message buffer interrupt flag */
03412             vuint16_t TBIFR:1;  /* transmit buffer interrupt flag */
03413         } B;
03414     } CIFRR_t;
03415     typedef union uSFCNTR {
03416         vuint16_t R;
03417         struct {
03418             vuint16_t SFEVB:4;  /* sync frames channel B, even cycle */
03419             vuint16_t SFEVA:4;  /* sync frames channel A, even cycle */
03420             vuint16_t SFODB:4;  /* sync frames channel B, odd cycle */
03421             vuint16_t SFODA:4;  /* sync frames channel A, odd cycle */
03422         } B;
03423     } SFCNTR_t;
03424 
03425     typedef union uSFTCCSR {
03426         vuint16_t R;
03427         struct {
03428             vuint16_t ELKT:1;   /* even cycle tables lock and unlock trigger */
03429             vuint16_t OLKT:1;   /* odd cycle tables lock and unlock trigger */
03430             vuint16_t CYCNUM:6; /* cycle number */
03431             vuint16_t ELKS:1;   /* even cycle tables lock status */
03432             vuint16_t OLKS:1;   /* odd cycle tables lock status */
03433             vuint16_t EVAL:1;   /* even cycle tables valid */
03434             vuint16_t OVAL:1;   /* odd cycle tables valid */
03435               vuint16_t:1;
03436             vuint16_t OPT:1;    /*one pair trigger */
03437             vuint16_t SDVEN:1;  /* sync frame deviation table enable */
03438             vuint16_t SIDEN:1;  /* sync frame ID table enable */
03439         } B;
03440     } SFTCCSR_t;
03441     typedef union uSFIDRFR {
03442         vuint16_t R;
03443         struct {
03444             vuint16_t:6;
03445             vuint16_t SYNFRID:10;       /* sync frame rejection ID */
03446         } B;
03447     } SFIDRFR_t;
03448 
03449     typedef union uTICCR {
03450         vuint16_t R;
03451         struct {
03452             vuint16_t:2;
03453             vuint16_t T2CFG:1;  /* timer 2 configuration */
03454             vuint16_t T2REP:1;  /* timer 2 repetitive mode */
03455               vuint16_t:1;
03456             vuint16_t T2SP:1;   /* timer 2 stop */
03457             vuint16_t T2TR:1;   /* timer 2 trigger */
03458             vuint16_t T2ST:1;   /* timer 2 state */
03459               vuint16_t:3;
03460             vuint16_t T1REP:1;  /* timer 1 repetitive mode */
03461               vuint16_t:1;
03462             vuint16_t T1SP:1;   /* timer 1 stop */
03463             vuint16_t T1TR:1;   /* timer 1 trigger */
03464             vuint16_t T1ST:1;   /* timer 1 state */
03465 
03466         } B;
03467     } TICCR_t;
03468     typedef union uTI1CYSR {
03469         vuint16_t R;
03470         struct {
03471             vuint16_t:2;
03472             vuint16_t TI1CYCVAL:6;      /* timer 1 cycle filter value */
03473               vuint16_t:2;
03474             vuint16_t TI1CYCMSK:6;      /* timer 1 cycle filter mask */
03475 
03476         } B;
03477     } TI1CYSR_t;
03478 
03479     typedef union uSSSR {
03480         vuint16_t R;
03481         struct {
03482             vuint16_t WMD:1;    /* write mode */
03483               vuint16_t:1;
03484             vuint16_t SEL:2;    /* static slot number */
03485               vuint16_t:1;
03486             vuint16_t SLOTNUMBER:11;    /* selector */
03487         } B;
03488     } SSSR_t;
03489 
03490     typedef union uSSCCR {
03491         vuint16_t R;
03492         struct {
03493             vuint16_t WMD:1;    /* write mode */
03494               vuint16_t:1;
03495             vuint16_t SEL:2;    /* selector */
03496               vuint16_t:1;
03497             vuint16_t CNTCFG:2; /* counter configuration */
03498             vuint16_t MCY:1;    /* multi cycle selection */
03499             vuint16_t VFR:1;    /* valid frame selection */
03500             vuint16_t SYF:1;    /* sync frame selection */
03501             vuint16_t NUF:1;    /* null frame selection  */
03502             vuint16_t SUF:1;    /* startup frame selection */
03503             vuint16_t STATUSMASK:4;     /* slot status mask */
03504         } B;
03505     } SSCCR_t;
03506     typedef union uSSR {
03507         vuint16_t R;
03508         struct {
03509             vuint16_t VFB:1;    /* valid frame on channel B */
03510             vuint16_t SYB:1;    /* valid sync frame on channel B */
03511             vuint16_t NFB:1;    /* valid null frame on channel B */
03512             vuint16_t SUB:1;    /* valid startup frame on channel B */
03513             vuint16_t SEB:1;    /* syntax error on channel B */
03514             vuint16_t CEB:1;    /* content error on channel B */
03515             vuint16_t BVB:1;    /* boundary violation on channel B */
03516             vuint16_t TCB:1;    /* tx conflict on channel B */
03517             vuint16_t VFA:1;    /* valid frame on channel A */
03518             vuint16_t SYA:1;    /* valid sync frame on channel A */
03519             vuint16_t NFA:1;    /* valid null frame on channel A */
03520             vuint16_t SUA:1;    /* valid startup frame on channel A */
03521             vuint16_t SEA:1;    /* syntax error on channel A */
03522             vuint16_t CEA:1;    /* content error on channel A */
03523             vuint16_t BVA:1;    /* boundary violation on channel A */
03524             vuint16_t TCA:1;    /* tx conflict on channel A */
03525         } B;
03526     } SSR_t;
03527     typedef union uMTSCFR {
03528         vuint16_t R;
03529         struct {
03530             vuint16_t MTE:1;    /* media access test symbol transmission enable */
03531               vuint16_t:1;
03532             vuint16_t CYCCNTMSK:6;      /* cycle counter mask */
03533               vuint16_t:2;
03534             vuint16_t CYCCNTVAL:6;      /* cycle counter value */
03535         } B;
03536     } MTSCFR_t;
03537 
03538     typedef union uRSBIR {
03539         vuint16_t R;
03540         struct {
03541             vuint16_t WMD:1;    /* write mode */
03542               vuint16_t:1;
03543             vuint16_t SEL:2;    /* selector */
03544               vuint16_t:5;
03545             vuint16_t RSBIDX:7; /* receive shadow buffer index */
03546         } B;
03547     } RSBIR_t;
03548 
03549     typedef union uRFDSR {
03550         vuint16_t R;
03551         struct {
03552             vuint16_t FIFODEPTH:8;      /* fifo depth */
03553               vuint16_t:1;
03554             vuint16_t ENTRYSIZE:7;      /* entry size */
03555         } B;
03556     } RFDSR_t;
03557 
03558     typedef union uRFRFCFR {
03559         vuint16_t R;
03560         struct {
03561             vuint16_t WMD:1;    /* write mode */
03562             vuint16_t IBD:1;    /* interval boundary */
03563             vuint16_t SEL:2;    /* filter number */
03564               vuint16_t:1;
03565             vuint16_t SID:11;   /* slot ID */
03566         } B;
03567     } RFRFCFR_t;
03568 
03569     typedef union uRFRFCTR {
03570         vuint16_t R;
03571         struct {
03572             vuint16_t:4;
03573             vuint16_t F3MD:1;   /* filter mode */
03574             vuint16_t F2MD:1;   /* filter mode */
03575             vuint16_t F1MD:1;   /* filter mode */
03576             vuint16_t F0MD:1;   /* filter mode */
03577               vuint16_t:4;
03578             vuint16_t F3EN:1;   /* filter enable */
03579             vuint16_t F2EN:1;   /* filter enable */
03580             vuint16_t F1EN:1;   /* filter enable */
03581             vuint16_t F0EN:1;   /* filter enable */
03582         } B;
03583     } RFRFCTR_t;
03584     typedef union uPCR0 {
03585         vuint16_t R;
03586         struct {
03587             vuint16_t ACTION_POINT_OFFSET:6;
03588             vuint16_t STATIC_SLOT_LENGTH:10;
03589         } B;
03590     } PCR0_t;
03591 
03592     typedef union uPCR1 {
03593         vuint16_t R;
03594         struct {
03595             vuint16_t:2;
03596             vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
03597         } B;
03598     } PCR1_t;
03599 
03600     typedef union uPCR2 {
03601         vuint16_t R;
03602         struct {
03603             vuint16_t MINISLOT_AFTER_ACTION_POINT:6;
03604             vuint16_t NUMBER_OF_STATIC_SLOTS:10;
03605         } B;
03606     } PCR2_t;
03607 
03608     typedef union uPCR3 {
03609         vuint16_t R;
03610         struct {
03611             vuint16_t WAKEUP_SYMBOL_RX_LOW:6;
03612             vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;
03613             vuint16_t COLDSTART_ATTEMPTS:5;
03614         } B;
03615     } PCR3_t;
03616 
03617     typedef union uPCR4 {
03618         vuint16_t R;
03619         struct {
03620             vuint16_t CAS_RX_LOW_MAX:7;
03621             vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
03622         } B;
03623     } PCR4_t;
03624 
03625     typedef union uPCR5 {
03626         vuint16_t R;
03627         struct {
03628             vuint16_t TSS_TRANSMITTER:4;
03629             vuint16_t WAKEUP_SYMBOL_TX_LOW:6;
03630             vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;
03631         } B;
03632     } PCR5_t;
03633 
03634     typedef union uPCR6 {
03635         vuint16_t R;
03636         struct {
03637             vuint16_t:1;
03638             vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
03639             vuint16_t MACRO_INITIAL_OFFSET_A:7;
03640         } B;
03641     } PCR6_t;
03642 
03643     typedef union uPCR7 {
03644         vuint16_t R;
03645         struct {
03646             vuint16_t DECODING_CORRECTION_B:9;
03647             vuint16_t MICRO_PER_MACRO_NOM_HALF:7;
03648         } B;
03649     } PCR7_t;
03650 
03651     typedef union uPCR8 {
03652         vuint16_t R;
03653         struct {
03654             vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
03655             vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
03656             vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;
03657         } B;
03658     } PCR8_t;
03659 
03660     typedef union uPCR9 {
03661         vuint16_t R;
03662         struct {
03663             vuint16_t MINISLOT_EXISTS:1;
03664             vuint16_t SYMBOL_WINDOW_EXISTS:1;
03665             vuint16_t OFFSET_CORRECTION_OUT:14;
03666         } B;
03667     } PCR9_t;
03668 
03669     typedef union uPCR10 {
03670         vuint16_t R;
03671         struct {
03672             vuint16_t SINGLE_SLOT_ENABLED:1;
03673             vuint16_t WAKEUP_CHANNEL:1;
03674             vuint16_t MACRO_PER_CYCLE:14;
03675         } B;
03676     } PCR10_t;
03677 
03678     typedef union uPCR11 {
03679         vuint16_t R;
03680         struct {
03681             vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;
03682             vuint16_t KEY_SLOT_USED_FOR_SYNC:1;
03683             vuint16_t OFFSET_CORRECTION_START:14;
03684         } B;
03685     } PCR11_t;
03686 
03687     typedef union uPCR12 {
03688         vuint16_t R;
03689         struct {
03690             vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
03691             vuint16_t KEY_SLOT_HEADER_CRC:11;
03692         } B;
03693     } PCR12_t;
03694 
03695     typedef union uPCR13 {
03696         vuint16_t R;
03697         struct {
03698             vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
03699             vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
03700         } B;
03701     } PCR13_t;
03702 
03703     typedef union uPCR14 {
03704         vuint16_t R;
03705         struct {
03706             vuint16_t RATE_CORRECTION_OUT:11;
03707             vuint16_t LISTEN_TIMEOUT_H:5;
03708         } B;
03709     } PCR14_t;
03710 
03711     typedef union uPCR15 {
03712         vuint16_t R;
03713         struct {
03714             vuint16_t LISTEN_TIMEOUT_L:16;
03715         } B;
03716     } PCR15_t;
03717 
03718     typedef union uPCR16 {
03719         vuint16_t R;
03720         struct {
03721             vuint16_t MACRO_INITIAL_OFFSET_B:7;
03722             vuint16_t NOISE_LISTEN_TIMEOUT_H:9;
03723         } B;
03724     } PCR16_t;
03725 
03726     typedef union uPCR17 {
03727         vuint16_t R;
03728         struct {
03729             vuint16_t NOISE_LISTEN_TIMEOUT_L:16;
03730         } B;
03731     } PCR17_t;
03732 
03733     typedef union uPCR18 {
03734         vuint16_t R;
03735         struct {
03736             vuint16_t WAKEUP_PATTERN:6;
03737             vuint16_t KEY_SLOT_ID:10;
03738         } B;
03739     } PCR18_t;
03740 
03741     typedef union uPCR19 {
03742         vuint16_t R;
03743         struct {
03744             vuint16_t DECODING_CORRECTION_A:9;
03745             vuint16_t PAYLOAD_LENGTH_STATIC:7;
03746         } B;
03747     } PCR19_t;
03748 
03749     typedef union uPCR20 {
03750         vuint16_t R;
03751         struct {
03752             vuint16_t MICRO_INITIAL_OFFSET_B:8;
03753             vuint16_t MICRO_INITIAL_OFFSET_A:8;
03754         } B;
03755     } PCR20_t;
03756 
03757     typedef union uPCR21 {
03758         vuint16_t R;
03759         struct {
03760             vuint16_t EXTERN_RATE_CORRECTION:3;
03761             vuint16_t LATEST_TX:13;
03762         } B;
03763     } PCR21_t;
03764 
03765     typedef union uPCR22 {
03766         vuint16_t R;
03767         struct {
03768             vuint16_t:1;
03769             vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
03770             vuint16_t MICRO_PER_CYCLE_H:4;
03771         } B;
03772     } PCR22_t;
03773 
03774     typedef union uPCR23 {
03775         vuint16_t R;
03776         struct {
03777             vuint16_t micro_per_cycle_l:16;
03778         } B;
03779     } PCR23_t;
03780 
03781     typedef union uPCR24 {
03782         vuint16_t R;
03783         struct {
03784             vuint16_t CLUSTER_DRIFT_DAMPING:5;
03785             vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
03786             vuint16_t MICRO_PER_CYCLE_MIN_H:4;
03787         } B;
03788     } PCR24_t;
03789 
03790     typedef union uPCR25 {
03791         vuint16_t R;
03792         struct {
03793             vuint16_t MICRO_PER_CYCLE_MIN_L:16;
03794         } B;
03795     } PCR25_t;
03796 
03797     typedef union uPCR26 {
03798         vuint16_t R;
03799         struct {
03800             vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
03801             vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
03802             vuint16_t MICRO_PER_CYCLE_MAX_H:4;
03803         } B;
03804     } PCR26_t;
03805 
03806     typedef union uPCR27 {
03807         vuint16_t R;
03808         struct {
03809             vuint16_t MICRO_PER_CYCLE_MAX_L:16;
03810         } B;
03811     } PCR27_t;
03812 
03813     typedef union uPCR28 {
03814         vuint16_t R;
03815         struct {
03816             vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
03817             vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
03818         } B;
03819     } PCR28_t;
03820 
03821     typedef union uPCR29 {
03822         vuint16_t R;
03823         struct {
03824             vuint16_t EXTERN_OFFSET_CORRECTION:3;
03825             vuint16_t MINISLOTS_MAX:13;
03826         } B;
03827     } PCR29_t;
03828 
03829     typedef union uPCR30 {
03830         vuint16_t R;
03831         struct {
03832             vuint16_t:12;
03833             vuint16_t SYNC_NODE_MAX:4;
03834         } B;
03835     } PCR30_t;
03836 
03837     typedef struct uMSG_BUFF_CCS {
03838         union {
03839             vuint16_t R;
03840             struct {
03841                 vuint16_t:1;
03842                 vuint16_t MCM:1;        /* message buffer commit mode */
03843                 vuint16_t MBT:1;        /* message buffer type */
03844                 vuint16_t MTD:1;        /* message buffer direction */
03845                 vuint16_t CMT:1;        /* commit for transmission */
03846                 vuint16_t EDT:1;        /* enable / disable trigger */
03847                 vuint16_t LCKT:1;       /* lock request trigger */
03848                 vuint16_t MBIE:1;       /* message buffer interrupt enable */
03849                   vuint16_t:3;
03850                 vuint16_t DUP:1;        /* data updated  */
03851                 vuint16_t DVAL:1;       /* data valid */
03852                 vuint16_t EDS:1;        /* lock status */
03853                 vuint16_t LCKS:1;       /* enable / disable status */
03854                 vuint16_t MBIF:1;       /* message buffer interrupt flag */
03855             } B;
03856         } MBCCSR;
03857         union {
03858             vuint16_t R;
03859             struct {
03860                 vuint16_t MTM:1;        /* message buffer transmission mode */
03861                 vuint16_t CHNLA:1;      /* channel assignement */
03862                 vuint16_t CHNLB:1;      /* channel assignement */
03863                 vuint16_t CCFE:1;       /* cycle counter filter enable */
03864                 vuint16_t CCFMSK:6;     /* cycle counter filter mask */
03865                 vuint16_t CCFVAL:6;     /* cycle counter filter value */
03866             } B;
03867         } MBCCFR;
03868         union {
03869             vuint16_t R;
03870             struct {
03871                 vuint16_t:5;
03872                 vuint16_t FID:11;       /* frame ID */
03873             } B;
03874         } MBFIDR;
03875 
03876         union {
03877             vuint16_t R;
03878             struct {
03879                 vuint16_t:9;
03880                 vuint16_t MBIDX:7;      /* message buffer index */
03881             } B;
03882         } MBIDXR;
03883     } MSG_BUFF_CCS_t;
03884     typedef union uSYSBADHR {
03885         vuint16_t R;
03886     } SYSBADHR_t;
03887     typedef union uSYSBADLR {
03888         vuint16_t R;
03889     } SYSBADLR_t;
03890     typedef union uPADR {
03891         vuint16_t R;
03892     } PADR_t;
03893     typedef union uPDAR {
03894         vuint16_t R;
03895     } PDAR_t;
03896     typedef union uCASERCR {
03897         vuint16_t R;
03898     } CASERCR_t;
03899     typedef union uCBSERCR {
03900         vuint16_t R;
03901     } CBSERCR_t;
03902     typedef union uCYCTR {
03903         vuint16_t R;
03904     } CYCTR_t;
03905     typedef union uMTCTR {
03906         vuint16_t R;
03907     } MTCTR_t;
03908     typedef union uSLTCTAR {
03909         vuint16_t R;
03910     } SLTCTAR_t;
03911     typedef union uSLTCTBR {
03912         vuint16_t R;
03913     } SLTCTBR_t;
03914     typedef union uRTCORVR {
03915         vuint16_t R;
03916     } RTCORVR_t;
03917     typedef union uOFCORVR {
03918         vuint16_t R;
03919     } OFCORVR_t;
03920     typedef union uSFTOR {
03921         vuint16_t R;
03922     } SFTOR_t;
03923     typedef union uSFIDAFVR {
03924         vuint16_t R;
03925     } SFIDAFVR_t;
03926     typedef union uSFIDAFMR {
03927         vuint16_t R;
03928     } SFIDAFMR_t;
03929     typedef union uNMVR {
03930         vuint16_t R;
03931     } NMVR_t;
03932     typedef union uNMVLR {
03933         vuint16_t R;
03934     } NMVLR_t;
03935     typedef union uT1MTOR {
03936         vuint16_t R;
03937     } T1MTOR_t;
03938     typedef union uTI2CR0 {
03939         vuint16_t R;
03940     } TI2CR0_t;
03941     typedef union uTI2CR1 {
03942         vuint16_t R;
03943     } TI2CR1_t;
03944     typedef union uSSCR {
03945         vuint16_t R;
03946     } SSCR_t;
03947     typedef union uRFSR {
03948         vuint16_t R;
03949     } RFSR_t;
03950     typedef union uRFSIR {
03951         vuint16_t R;
03952     } RFSIR_t;
03953     typedef union uRFARIR {
03954         vuint16_t R;
03955     } RFARIR_t;
03956     typedef union uRFBRIR {
03957         vuint16_t R;
03958     } RFBRIR_t;
03959     typedef union uRFMIDAFVR {
03960         vuint16_t R;
03961     } RFMIDAFVR_t;
03962     typedef union uRFMIAFMR {
03963         vuint16_t R;
03964     } RFMIAFMR_t;
03965     typedef union uRFFIDRFVR {
03966         vuint16_t R;
03967     } RFFIDRFVR_t;
03968     typedef union uRFFIDRFMR {
03969         vuint16_t R;
03970     } RFFIDRFMR_t;
03971     typedef union uLDTXSLAR {
03972         vuint16_t R;
03973     } LDTXSLAR_t;
03974     typedef union uLDTXSLBR {
03975         vuint16_t R;
03976     } LDTXSLBR_t;
03977 
03978     typedef struct FR_tag {
03979         volatile MVR_t MVR;     /*module version register *//*0  */
03980         volatile MCR_t MCR;     /*module configuration register *//*2  */
03981         volatile SYSBADHR_t SYSBADHR;   /*system memory base address high register *//*4        */
03982         volatile SYSBADLR_t SYSBADLR;   /*system memory base address low register *//*6         */
03983         volatile STBSCR_t STBSCR;       /*strobe signal control register *//*8      */
03984         volatile STBPCR_t STBPCR;       /*strobe port control register *//*A        */
03985         volatile MBDSR_t MBDSR; /*message buffer data size register *//*C  */
03986         volatile MBSSUTR_t MBSSUTR;     /*message buffer segment size and utilization register *//*E  */
03987         volatile PADR_t PADR;   /*PE address register *//*10 */
03988         volatile PDAR_t PDAR;   /*PE data register *//*12 */
03989         volatile POCR_t POCR;   /*Protocol operation control register *//*14 */
03990         volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
03991         volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
03992         volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
03993         volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
03994         volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
03995         volatile CHIERFR_t CHIERFR;     /*CHI error flag register *//*20 */
03996         volatile MBIVEC_t MBIVEC;       /*message buffer interrupt vector register *//*22 */
03997         volatile CASERCR_t CASERCR;     /*channel A status error counter register *//*24 */
03998         volatile CBSERCR_t CBSERCR;     /*channel B status error counter register *//*26 */
03999         volatile PSR0_t PSR0;   /*protocol status register 0 *//*28 */
04000         volatile PSR1_t PSR1;   /*protocol status register 1 *//*2A */
04001         volatile PSR2_t PSR2;   /*protocol status register 2 *//*2C */
04002         volatile PSR3_t PSR3;   /*protocol status register 3 *//*2E */
04003         volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
04004         volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
04005         volatile SLTCTAR_t SLTCTAR;     /*slot counter channel A register *//*34 */
04006         volatile SLTCTBR_t SLTCTBR;     /*slot counter channel B register *//*36 */
04007         volatile RTCORVR_t RTCORVR;     /*rate correction value register *//*38 */
04008         volatile OFCORVR_t OFCORVR;     /*offset correction value register *//*3A */
04009         volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
04010         vuint16_t reserved3[1]; /*3E */
04011         volatile SFCNTR_t SFCNTR;       /*sync frame counter register *//*40 */
04012         volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
04013         volatile SFTCCSR_t SFTCCSR;     /*sync frame table configuration, control, status register *//*44 */
04014         volatile SFIDRFR_t SFIDRFR;     /*sync frame ID rejection filter register *//*46 */
04015         volatile SFIDAFVR_t SFIDAFVR;   /*sync frame ID acceptance filter value regiater *//*48 */
04016         volatile SFIDAFMR_t SFIDAFMR;   /*sync frame ID acceptance filter mask register *//*4A */
04017         volatile NMVR_t NMVR[6];        /*network management vector registers (12 bytes) *//*4C */
04018         volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
04019         volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
04020         volatile TI1CYSR_t TI1CYSR;     /*timer 1 cycle set register *//*5C */
04021         volatile T1MTOR_t T1MTOR;       /*timer 1 macrotick offset register *//*5E */
04022         volatile TI2CR0_t TI2CR0;       /*timer 2 configuration register 0 *//*60 */
04023         volatile TI2CR1_t TI2CR1;       /*timer 2 configuration register 1 *//*62 */
04024         volatile SSSR_t SSSR;   /*slot status selection register *//*64 */
04025         volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
04026         volatile SSR_t SSR[8];  /*slot status registers 0-7 *//*68 */
04027         volatile SSCR_t SSCR[4];        /*slot status counter registers 0-3 *//*78 */
04028         volatile MTSCFR_t MTSACFR;      /*mts a config register *//*80 */
04029         volatile MTSCFR_t MTSBCFR;      /*mts b config register *//*82 */
04030         volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
04031         volatile RFSR_t RFSR;   /*receive fifo selection register *//*86 */
04032         volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
04033         volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
04034         volatile RFARIR_t RFARIR;       /*receive fifo a read index register *//*8C */
04035         volatile RFBRIR_t RFBRIR;       /*receive fifo b read index register *//*8E */
04036         volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
04037         volatile RFMIAFMR_t RFMIAFMR;   /*receive fifo message ID acceptance filter mask register *//*92 */
04038         volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
04039         volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
04040         volatile RFRFCFR_t RFRFCFR;     /*receive fifo range filter configuration register *//*98 */
04041         volatile RFRFCTR_t RFRFCTR;     /*receive fifo range filter control register *//*9A */
04042         volatile LDTXSLAR_t LDTXSLAR;   /*last dynamic transmit slot channel A register *//*9C */
04043         volatile LDTXSLBR_t LDTXSLBR;   /*last dynamic transmit slot channel B register *//*9E */
04044         volatile PCR0_t PCR0;   /*protocol configuration register 0 *//*A0 */
04045         volatile PCR1_t PCR1;   /*protocol configuration register 1 *//*A2 */
04046         volatile PCR2_t PCR2;   /*protocol configuration register 2 *//*A4 */
04047         volatile PCR3_t PCR3;   /*protocol configuration register 3 *//*A6 */
04048         volatile PCR4_t PCR4;   /*protocol configuration register 4 *//*A8 */
04049         volatile PCR5_t PCR5;   /*protocol configuration register 5 *//*AA */
04050         volatile PCR6_t PCR6;   /*protocol configuration register 6 *//*AC */
04051         volatile PCR7_t PCR7;   /*protocol configuration register 7 *//*AE */
04052         volatile PCR8_t PCR8;   /*protocol configuration register 8 *//*B0 */
04053         volatile PCR9_t PCR9;   /*protocol configuration register 9 *//*B2 */
04054         volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
04055         volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
04056         volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
04057         volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
04058         volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
04059         volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
04060         volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
04061         volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
04062         volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
04063         volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
04064         volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
04065         volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
04066         volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
04067         volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
04068         volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
04069         volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
04070         volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
04071         volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
04072         volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
04073         volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
04074         volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
04075         vuint16_t reserved2[17];
04076         volatile MSG_BUFF_CCS_t MBCCS[128];     /* message buffer configuration, control & status registers 0-31 *//*100 */
04077     } FR_tag_t;
04078 
04079     typedef union uF_HEADER     /* frame header */
04080     {
04081         struct {
04082             vuint16_t:5;
04083             vuint16_t HDCRC:11; /* Header CRC */
04084               vuint16_t:2;
04085             vuint16_t CYCCNT:6; /* Cycle Count */
04086               vuint16_t:1;
04087             vuint16_t PLDLEN:7; /* Payload Length */
04088               vuint16_t:1;
04089             vuint16_t PPI:1;    /* Payload Preamble Indicator */
04090             vuint16_t NUF:1;    /* Null Frame Indicator */
04091             vuint16_t SYF:1;    /* Sync Frame Indicator */
04092             vuint16_t SUF:1;    /* Startup Frame Indicator */
04093             vuint16_t FID:11;   /* Frame ID */
04094         } B;
04095         vuint16_t WORDS[3];
04096     } F_HEADER_t;
04097     typedef union uS_STSTUS     /* slot status */
04098     {
04099         struct {
04100             vuint16_t VFB:1;    /* Valid Frame on channel B */
04101             vuint16_t SYB:1;    /* Sync Frame Indicator channel B */
04102             vuint16_t NFB:1;    /* Null Frame Indicator channel B */
04103             vuint16_t SUB:1;    /* Startup Frame Indicator channel B */
04104             vuint16_t SEB:1;    /* Syntax Error on channel B */
04105             vuint16_t CEB:1;    /* Content Error on channel B */
04106             vuint16_t BVB:1;    /* Boundary Violation on channel B */
04107             vuint16_t CH:1;     /* Channel */
04108             vuint16_t VFA:1;    /* Valid Frame on channel A */
04109             vuint16_t SYA:1;    /* Sync Frame Indicator channel A */
04110             vuint16_t NFA:1;    /* Null Frame Indicator channel A */
04111             vuint16_t SUA:1;    /* Startup Frame Indicator channel A */
04112             vuint16_t SEA:1;    /* Syntax Error on channel A */
04113             vuint16_t CEA:1;    /* Content Error on channel A */
04114             vuint16_t BVA:1;    /* Boundary Violation on channel A */
04115               vuint16_t:1;
04116         } RX;
04117         struct {
04118             vuint16_t VFB:1;    /* Valid Frame on channel B */
04119             vuint16_t SYB:1;    /* Sync Frame Indicator channel B */
04120             vuint16_t NFB:1;    /* Null Frame Indicator channel B */
04121             vuint16_t SUB:1;    /* Startup Frame Indicator channel B */
04122             vuint16_t SEB:1;    /* Syntax Error on channel B */
04123             vuint16_t CEB:1;    /* Content Error on channel B */
04124             vuint16_t BVB:1;    /* Boundary Violation on channel B */
04125             vuint16_t TCB:1;    /* Tx Conflict on channel B */
04126             vuint16_t VFA:1;    /* Valid Frame on channel A */
04127             vuint16_t SYA:1;    /* Sync Frame Indicator channel A */
04128             vuint16_t NFA:1;    /* Null Frame Indicator channel A */
04129             vuint16_t SUA:1;    /* Startup Frame Indicator channel A */
04130             vuint16_t SEA:1;    /* Syntax Error on channel A */
04131             vuint16_t CEA:1;    /* Content Error on channel A */
04132             vuint16_t BVA:1;    /* Boundary Violation on channel A */
04133             vuint16_t TCA:1;    /* Tx Conflict on channel A */
04134         } TX;
04135         vuint16_t R;
04136     } S_STATUS_t;
04137 
04138     typedef struct uMB_HEADER   /* message buffer header */
04139     {
04140         F_HEADER_t FRAME_HEADER;
04141         vuint16_t DATA_OFFSET;
04142         S_STATUS_t SLOT_STATUS;
04143     } MB_HEADER_t;
04144 
04145 /* Define memories */
04146 
04147 #define SRAM_START  0x40000000
04148 #define SRAM_SIZE      0x10000
04149 #define SRAM_END    0x4000FFFF
04150 
04151 #define FLASH_START         0x0
04152 #define FLASH_SIZE      0x100000
04153 #define FLASH_END       0xFFFFF
04154 
04155 /* Define instances of modules */
04156 #define SEMA4     (*( struct SEMA4_tag *)     0xFFF10000)
04157 #define MPU       (*( struct MPU_tag *)       0xFFF14000)
04158 
04159 #define MCM       (*( struct MCM_tag *)       0xFFF40000)
04160 #define EDMA      (*( struct EDMA_tag *)      0xFFF44000)
04161 #define INTC      (*( struct INTC_tag *)      0xFFF48000)
04162 
04163 #define EQADC     (*( struct EQADC_tag *)     0xFFF80000)
04164 
04165 #define I2C       (*( struct I2C_tag *)       0xFFF88000)
04166 
04167 #define DSPI_A    (*( struct DSPI_tag *)      0xFFF90000)
04168 #define DSPI_B    (*( struct DSPI_tag *)      0xFFF94000)
04169 #define DSPI_C    (*( struct DSPI_tag *)      0xFFF98000)
04170 
04171 #define ESCI_A    (*( struct ESCI_tag *)      0xFFFA0000)
04172 #define ESCI_B    (*( struct ESCI_tag *)      0xFFFA4000)
04173 #define ESCI_C    (*( struct ESCI_tag *)      0xFFFA8000)
04174 #define ESCI_D    (*( struct ESCI_tag *)      0xFFFAC000)
04175 #define ESCI_E    (*( struct ESCI_tag *)      0xFFFB0000)
04176 #define ESCI_F    (*( struct ESCI_tag *)      0xFFFB4000)
04177 #define ESCI_G    (*( struct ESCI_tag *)      0xFFFB8000)
04178 #define ESCI_H    (*( struct ESCI_tag *)      0xFFFBC000)
04179 
04180 #define CAN_A     (*( struct FLEXCAN_tag *)  0xFFFC0000)
04181 #define CAN_B     (*( struct FLEXCAN_tag *)  0xFFFC4000)
04182 #define CAN_C     (*( struct FLEXCAN_tag *)  0xFFFC8000)
04183 #define CAN_D     (*( struct FLEXCAN_tag *)  0xFFFCC000)
04184 #define CAN_E     (*( struct FLEXCAN_tag *)  0xFFFD0000)
04185 #define CAN_F     (*( struct FLEXCAN_tag *)  0xFFFD4000)
04186 #define FR        (*( struct FR_tag *)       0xFFFD8000)
04187 #define DMAMUX    (*( struct DMAMUX_tag *)   0xFFFDC000)
04188 #define PIT       (*( struct PIT_tag *)      0xFFFE0000)
04189 #define EMIOS     (*( struct EMIOS_tag *)    0xFFFE4000)
04190 #define SIU       (*( struct SIU_tag *)      0xFFFE8000)
04191 #define CRP       (*( struct CRP_tag *)      0xFFFEC000)
04192 #define FMPLL     (*( struct FMPLL_tag *)    0xFFFF0000)
04193 #define EBI       (*( struct EBI_tag *)      0xFFFF4000)
04194 #define FLASH     (*( struct FLASH_tag *)    0xFFFF8000)
04195 
04196 #ifdef __MWERKS__
04197 #pragma pop
04198 #endif
04199 
04200 #ifdef  __cplusplus
04201 }
04202 #endif
04203 #endif                          /* ifdef _MPC5516_H */